Sean Cross c8e8f254ca targets: fomu: add USBSoC and default to heap placer ... The heap placer is important enough that we should just make it the default. Also, add a `USBSoC` that includes the required interrupt table, as this must be specified prior to calling `__init__()`. Signed-off-by: Sean Cross <sean@xobs.io>		2019-09-17 17:08:05 +08:00
..
__init__.py	import: allow importing directly from litex_boards.platforms or litex_boards.targets	2019-09-03 15:30:20 +02:00
aller.py	partner: aller/nereid/tagus fix copyright (Rohit Singh as main author), do some cosmetic	2019-09-02 11:43:30 +02:00
c10lprefkit.py	add initial Trenz Cyclone 10 LP RefKit support with SDRAM/HyperRAM/Ethernet	2019-09-10 11:32:29 +02:00
fomu.py	targets: fomu: add USBSoC and default to heap placer	2019-09-17 17:08:05 +08:00
nereid.py	partner/targets/nereid: MT8KTF51264 now in LiteDRAM	2019-09-09 08:50:06 +02:00
netv2.py	partner/netv2: switch to MVP (K4B2G1646F instead of MT41J128M16)	2019-09-12 09:52:13 +02:00
tagus.py	partner: aller/nereid/tagus fix copyright (Rohit Singh as main author), do some cosmetic	2019-09-02 11:43:30 +02:00
trellisboard.py	targets: import platforms from litex_boards.platforms	2019-08-26 09:09:40 +02:00
ulx3s.py	targets: import platforms from litex_boards.platforms	2019-08-26 09:09:40 +02:00