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__init__.py
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Avoid Official/Partner/Community differentiation: use same directory for all platforms/targets.
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2020-02-03 09:36:30 +01:00 |
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ac701.py
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targets/xilinx: use generic name for idelay clk (avoid clk200, clk400, etc...) since we somtimes want to change it.
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2020-10-13 12:10:29 +02:00 |
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acorn_cle_215.py
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targets/xilinx: use generic name for idelay clk (avoid clk200, clk400, etc...) since we somtimes want to change it.
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2020-10-13 12:10:29 +02:00 |
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aller.py
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targets/xilinx: use generic name for idelay clk (avoid clk200, clk400, etc...) since we somtimes want to change it.
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2020-10-13 12:10:29 +02:00 |
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alveo_u250.py
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targets/xilinx: use generic name for idelay clk (avoid clk200, clk400, etc...) since we somtimes want to change it.
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2020-10-13 12:10:29 +02:00 |
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arty.py
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targets/xilinx: use generic name for idelay clk (avoid clk200, clk400, etc...) since we somtimes want to change it.
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2020-10-13 12:10:29 +02:00 |
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arty_s7.py
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targets/xilinx: use generic name for idelay clk (avoid clk200, clk400, etc...) since we somtimes want to change it.
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2020-10-13 12:10:29 +02:00 |
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c10lprefkit.py
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general: add SPDX License identifier to header and specify files are part of LiteX-Boards.
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2020-08-23 15:00:17 +02:00 |
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camlink_4k.py
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targets: simplify clocking on iCE40/ECP5 targets (AsyncResetSynchronizer now integrated in PLL).
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2020-09-01 13:38:32 +02:00 |
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colorlight_5a_75x.py
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targets/colorlight_5a_75x: make Ethernet PHY selectable, cast sys_clk_freq to int for Wishbone
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2020-09-02 22:08:45 +02:00 |
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crosslink_nx_evn.py
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crosslink_nx_evn: Improve documentation on UART jumpers
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2020-09-05 09:58:28 +01:00 |
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crosslink_nx_vip.py
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crosslink_nx_vip: Add HyperRAM support
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2020-10-22 09:15:40 +01:00 |
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de0nano.py
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targets/de0nano: set sys2x_ps phase to 180° for sdram_rate=1:2.
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2020-08-24 09:28:51 +02:00 |
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de1soc.py
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general: add SPDX License identifier to header and specify files are part of LiteX-Boards.
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2020-08-23 15:00:17 +02:00 |
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de2_115.py
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general: add SPDX License identifier to header and specify files are part of LiteX-Boards.
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2020-08-23 15:00:17 +02:00 |
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de10lite.py
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general: add SPDX License identifier to header and specify files are part of LiteX-Boards.
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2020-08-23 15:00:17 +02:00 |
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de10nano.py
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general: add SPDX License identifier to header and specify files are part of LiteX-Boards.
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2020-08-23 15:00:17 +02:00 |
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ecp5_evn.py
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targets: simplify clocking on iCE40/ECP5 targets (AsyncResetSynchronizer now integrated in PLL).
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2020-09-01 13:38:32 +02:00 |
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ecpix5.py
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targets: simplify clocking on iCE40/ECP5 targets (AsyncResetSynchronizer now integrated in PLL).
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2020-09-01 13:38:32 +02:00 |
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fk33.py
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targets/pcie: update timing_constraints (now provided by the .xci).
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2020-09-24 09:50:55 +02:00 |
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fomu.py
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targets/fomu: base it on iCEBreaker target + USB-ACM.
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2020-10-06 11:39:30 +02:00 |
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genesys2.py
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targets/xilinx: use generic name for idelay clk (avoid clk200, clk400, etc...) since we somtimes want to change it.
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2020-10-13 12:10:29 +02:00 |
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hadbadge.py
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targets: simplify clocking on iCE40/ECP5 targets (AsyncResetSynchronizer now integrated in PLL).
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2020-09-01 13:38:32 +02:00 |
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icebreaker.py
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targets/icebreaker: simplify, update PLL/API and BIOS execution from SPI Flash.
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2020-09-01 12:58:13 +02:00 |
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kc705.py
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targets/kc705: simplify SATA using LiteX's add_sata integration method.
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2020-10-29 10:16:40 +01:00 |
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kcu105.py
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targets/xilinx: use generic name for idelay clk (avoid clk200, clk400, etc...) since we somtimes want to change it.
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2020-10-13 12:10:29 +02:00 |
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kx2.py
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targets/xilinx: use generic name for idelay clk (avoid clk200, clk400, etc...) since we somtimes want to change it.
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2020-10-13 12:10:29 +02:00 |
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linsn_rv901t.py
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general: add SPDX License identifier to header and specify files are part of LiteX-Boards.
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2020-08-23 15:00:17 +02:00 |
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logicbone.py
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targets/xilinx: use generic name for idelay clk (avoid clk200, clk400, etc...) since we somtimes want to change it.
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2020-10-13 12:10:29 +02:00 |
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mercury_xu5.py
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targets/xilinx: use generic name for idelay clk (avoid clk200, clk400, etc...) since we somtimes want to change it.
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2020-10-13 12:10:29 +02:00 |
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mimas_a7.py
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targets/xilinx: use generic name for idelay clk (avoid clk200, clk400, etc...) since we somtimes want to change it.
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2020-10-13 12:10:29 +02:00 |
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minispartan6.py
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general: add SPDX License identifier to header and specify files are part of LiteX-Boards.
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2020-08-23 15:00:17 +02:00 |
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mist.py
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mist: add copyrights.
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2020-10-22 10:48:58 +02:00 |
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nereid.py
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targets/xilinx: use generic name for idelay clk (avoid clk200, clk400, etc...) since we somtimes want to change it.
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2020-10-13 12:10:29 +02:00 |
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netv2.py
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targets/xilinx: use generic name for idelay clk (avoid clk200, clk400, etc...) since we somtimes want to change it.
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2020-10-13 12:10:29 +02:00 |
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nexys4ddr.py
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targets/xilinx: use generic name for idelay clk (avoid clk200, clk400, etc...) since we somtimes want to change it.
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2020-10-13 12:10:29 +02:00 |
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nexys_video.py
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targets/xilinx: use generic name for idelay clk (avoid clk200, clk400, etc...) since we somtimes want to change it.
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2020-10-13 12:10:29 +02:00 |
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orangecrab.py
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targets/orangecrab: add fallback to bootloader when usr_btn is pressed for 1 second.
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2020-09-01 16:22:32 +02:00 |
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pano_logic_g2.py
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general: add SPDX License identifier to header and specify files are part of LiteX-Boards.
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2020-08-23 15:00:17 +02:00 |
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pipistrello.py
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general: add SPDX License identifier to header and specify files are part of LiteX-Boards.
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2020-08-23 15:00:17 +02:00 |
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simple.py
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general: add SPDX License identifier to header and specify files are part of LiteX-Boards.
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2020-08-23 15:00:17 +02:00 |
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tagus.py
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targets/xilinx: use generic name for idelay clk (avoid clk200, clk400, etc...) since we somtimes want to change it.
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2020-10-13 12:10:29 +02:00 |
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tec0117.py
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don't verify erase, very slow
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2020-10-01 08:41:16 +02:00 |
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trellisboard.py
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targets: simplify clocking on iCE40/ECP5 targets (AsyncResetSynchronizer now integrated in PLL).
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2020-09-01 13:38:32 +02:00 |
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ulx3s.py
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ulx3s: add 1.7 and 2.0 revisions support.
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2020-10-12 13:23:26 +02:00 |
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vc707.py
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targets/xilinx: use generic name for idelay clk (avoid clk200, clk400, etc...) since we somtimes want to change it.
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2020-10-13 12:10:29 +02:00 |
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vcu118.py
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targets/xilinx: use generic name for idelay clk (avoid clk200, clk400, etc...) since we somtimes want to change it.
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2020-10-13 12:10:29 +02:00 |
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versa_ecp5.py
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versa_ecp5: Add --eth-phy to select ethernet phy
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2020-10-09 23:56:16 +02:00 |
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xcu1525.py
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targets/xilinx: use generic name for idelay clk (avoid clk200, clk400, etc...) since we somtimes want to change it.
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2020-10-13 12:10:29 +02:00 |
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zcu104.py
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targets/xilinx: use generic name for idelay clk (avoid clk200, clk400, etc...) since we somtimes want to change it.
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2020-10-13 12:10:29 +02:00 |
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zybo_z7.py
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general: add SPDX License identifier to header and specify files are part of LiteX-Boards.
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2020-08-23 15:00:17 +02:00 |
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