145 lines
5.7 KiB
Python
Executable File
145 lines
5.7 KiB
Python
Executable File
#!/usr/bin/env python3
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#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2021 Derek Mulcahy <derekmulcahy@gmail.com>
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# Copyright (c) 2019-2020 Florent Kermarrec <florent@enjoy-digital.fr>
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# SPDX-License-Identifier: BSD-2-Clause
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import os
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from migen import *
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from litex_boards.platforms import snickerdoodle
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from litex.build.xilinx.vivado import vivado_build_args, vivado_build_argdict
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from litex.soc.interconnect import axi
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from litex.soc.interconnect import wishbone
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from litex.soc.cores.clock import *
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.builder import *
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from litex.soc.cores.led import LedChaser
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# UTILS ---------------------------------------------------------------------------------------------
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def load_ps7(soc, xci_file):
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odir = os.path.join("build", "snickerdoodle", "gateware", "xci")
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os.makedirs(odir, exist_ok=True)
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file = "snickerdoodle_ps7.xci"
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dst = os.path.join(odir, file)
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if xci_file is None:
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src = "https://technicaltoys-support.s3.amazonaws.com/xci/" + file
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os.system("wget " + src + " -O " + dst)
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else:
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os.system("cp -p " + xci_file + " " + dst)
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soc.cpu.set_ps7_xci(dst)
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# CRG ----------------------------------------------------------------------------------------------
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class _CRG(Module):
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def __init__(self, platform, sys_clk_freq, use_ps7_clk=False):
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self.rst = Signal()
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self.clock_domains.cd_sys = ClockDomain()
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# # #
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if use_ps7_clk:
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assert sys_clk_freq == 100e6
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self.comb += ClockSignal("sys").eq(ClockSignal("ps7"))
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self.comb += ResetSignal("sys").eq(ResetSignal("ps7") | self.rst)
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else:
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self.submodules.pll = pll = S7MMCM(speedgrade=-1)
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self.comb += pll.reset.eq(self.rst)
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pll.register_clkin(platform.request(platform.default_clk_name),
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platform.default_clk_freq)
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pll.create_clkout(self.cd_sys, sys_clk_freq)
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# Ignore sys_clk to pll.clkin path created by SoC's rst.
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platform.add_false_path_constraints(self.cd_sys.clk, pll.clkin)
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# BaseSoC ------------------------------------------------------------------------------------------
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class BaseSoC(SoCCore):
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def __init__(self, variant="z7-10", sys_clk_freq=int(100e6), with_led_chaser=True,
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ext_clk_freq = None,
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xci_file = None,
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**kwargs):
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platform = snickerdoodle.Platform(variant=variant)
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if ext_clk_freq:
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platform.default_clk_freq = ext_clk_freq
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platform.default_clk_period = 1e9 / ext_clk_freq
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if kwargs.get("cpu_type", None) == "zynq7000":
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kwargs["integrated_sram_size"] = 0
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kwargs["with_uart"] = False
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self.mem_map = {"csr": 0x4000_0000} # Zynq GP0 default
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# SoCCore ----------------------------------------------------------------------------------
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SoCCore.__init__(self, platform, sys_clk_freq,
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ident = "LiteX SoC on Snickerdoodle",
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**kwargs)
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# Zynq7000 Integration ---------------------------------------------------------------------
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if kwargs.get("cpu_type", None) == "zynq7000":
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load_ps7(self, xci_file)
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# Connect AXI GP0 to the SoC with base address of 0x43c00000 (default one)
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wb_gp0 = wishbone.Interface()
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self.submodules += axi.AXI2Wishbone(
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axi = self.cpu.add_axi_gp_master(),
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wishbone = wb_gp0,
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base_address = self.mem_map['csr'])
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self.add_wb_master(wb_gp0)
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use_ps7_clk = True
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else:
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use_ps7_clk = False
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# CRG --------------------------------------------------------------------------------------
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self.submodules.crg = _CRG(platform, sys_clk_freq, use_ps7_clk)
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# Leds -------------------------------------------------------------------------------------
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if with_led_chaser:
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self.submodules.leds = LedChaser(
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pads = platform.request_all("user_led"),
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sys_clk_freq = sys_clk_freq)
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# Build --------------------------------------------------------------------------------------------
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def main():
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from litex.soc.integration.soc import LiteXSoCArgumentParser
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parser = LiteXSoCArgumentParser(description="LiteX SoC on Snickerdoodle")
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target_group = parser.add_argument_group(title="Target options")
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target_group.add_argument("--build", action="store_true", help="Build bitstream.")
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target_group.add_argument("--load", action="store_true", help="Load bitstream.")
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target_group.add_argument("--variant", default="z7-10", help="Board variant (z7-10 or z7-20).")
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target_group.add_argument("--ext-clk-freq", default=10e6, type=float, help="External Clock Frequency.")
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target_group.add_argument("--sys-clk-freq", default=100e6, type=float, help="System clock frequency.")
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target_group.add_argument("--xci-file", help="XCI file for PS7 configuration.")
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target_group.add_argument("--target", help="Vivado programmer target.")
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builder_args(parser)
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soc_core_args(parser)
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vivado_build_args(parser)
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args = parser.parse_args()
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soc = BaseSoC(
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variant = args.variant,
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sys_clk_freq = args.sys_clk_freq,
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ext_clk_freq = args.ext_clk_freq,
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xci_file = args.xci_file,
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**soc_core_argdict(args)
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)
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builder = Builder(soc, **builder_argdict(args))
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builder.build(**vivado_build_argdict(args), run=args.build)
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if args.load:
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prog = soc.platform.create_programmer()
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prog.load_bitstream(builder.get_bitstream_filename(mode="sram"), target=args.target, device=1)
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if __name__ == "__main__":
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main()
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