114 lines
4.4 KiB
Python
Executable File
114 lines
4.4 KiB
Python
Executable File
#!/usr/bin/env python3
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#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2021 Florent Kermarrec <florent@enjoy-digital.fr>
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# Copyright (c) 2021 Gwenhael Goavec-Merou <gwenhael.goavec-merou@trabucayre.com>
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# SPDX-License-Identifier: BSD-2-Clause
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import os
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from migen import *
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from litex_boards.platforms import quicklogic_quickfeather
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from litex.soc.integration.soc import SoCRegion
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.builder import *
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from litex.soc.cores.led import LedChaser
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from litex.soc.cores.gpio import *
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# CRG ----------------------------------------------------------------------------------------------
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class _CRG(Module):
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def __init__(self, platform, with_eos_s3=False):
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self.rst = Signal()
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self.clock_domains.cd_sys = ClockDomain()
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# # #
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if with_eos_s3:
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# Use clocks generated by the EOS-S3 CPU.
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self.comb += ClockSignal("sys").eq(ClockSignal("eos_s3_0"))
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self.comb += ResetSignal("sys").eq(ResetSignal("eos_s3_0") | self.rst)
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else:
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# Use clocks generated by the qlal4s3b_cell_macro.
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class Open(Signal): pass
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self.specials += Instance("qlal4s3b_cell_macro",
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o_Sys_Clk0 = self.cd_sys.clk,
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o_Sys_Clk0_Rst = self.cd_sys.rst,
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o_Sys_Clk1 = Open(),
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o_Sys_Clk1_Rst = Open(),
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)
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# BaseSoC ------------------------------------------------------------------------------------------
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class BaseSoC(SoCCore):
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def __init__(self, sys_clk_freq=int(10e6), with_led_chaser=True, with_gpio_in=True, **kwargs):
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platform = quicklogic_quickfeather.Platform()
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# SoCCore ----------------------------------------------------------------------------------
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kwargs["with_uart"] = False
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if kwargs.get("cpu_type", None) == "eos_s3":
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kwargs['integrated_sram_size'] = 0
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SoCCore.__init__(self, platform, sys_clk_freq,
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ident = "LiteX SoC on QuickLogic QuickFeather",
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**kwargs)
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if kwargs.get("cpu_type", None) == "eos_s3":
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# in fact SRAM starts at 0x2000_0000 - but for some reason
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# this does not work and most QORC SDK linker scripts
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# use 0x2002_7000 + 0x0003_c800
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self.bus.add_region("sram", SoCRegion(
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origin=0x2002_7000,
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size=0x0003_c800)
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)
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self.bus.add_region("rom", SoCRegion(
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origin=self.mem_map["rom"],
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size=4 * 128 * 1024,
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linker=True)
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)
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# CRG --------------------------------------------------------------------------------------
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self.submodules.crg = _CRG(platform, with_eos_s3=kwargs["cpu_type"] == "eos_s3")
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# Leds -------------------------------------------------------------------------------------
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if with_led_chaser:
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self.submodules.leds = LedChaser(
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pads = platform.request_all("user_led"),
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sys_clk_freq = sys_clk_freq)
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# GPIOIn (Interrupt test) ------------------------------------------------------------------
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if with_gpio_in:
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self.submodules.gpio = GPIOIn(platform.request_all("user_btn_n"), with_irq=True)
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if kwargs["cpu_type"] == "eos_s3":
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self.irq.add("gpio", use_loc_if_exists=True)
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# Build --------------------------------------------------------------------------------------------
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def main():
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from litex.soc.integration.soc import LiteXSoCArgumentParser
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parser = LiteXSoCArgumentParser(description="LiteX SoC on QuickLogic QuickFeather")
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target_group = parser.add_argument_group(title="Target options")
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target_group.add_argument("--build", action="store_true", help="Build bitstream.")
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soc_core_args(parser)
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parser.set_defaults(cpu_type="eos_s3")
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args = parser.parse_args()
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soc = BaseSoC(**soc_core_argdict(args))
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builder = Builder(soc)
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if args.cpu_type == "eos_s3":
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libeos_path = os.path.join(os.path.dirname(os.path.abspath(__file__)), "libeos")
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if not os.path.exists(libeos_path):
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os.system("wget -nc https://github.com/litex-hub/litex-boards/files/7880350/libeos.zip")
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os.system(f"unzip libeos.zip -d {libeos_path}")
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builder.add_software_package("libeos", src_dir=libeos_path)
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builder.add_software_library("libeos")
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builder.build(run=args.build)
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if __name__ == "__main__":
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main()
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