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Do Viet Thanh ec7a5c4c0b Correct DDR4 IO Banks of Xilinx Alveo U200 2023-02-14 06:40:12 +07:00
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platforms Correct DDR4 IO Banks of Xilinx Alveo U200 2023-02-14 06:40:12 +07:00
prog Add initial LimeSDR Mini V2 support (With SoC + USB3 (FT245PHYSynchronous)). 2022-05-03 19:04:06 +02:00
targets Add support for Xilinx Alveo U200 2023-01-17 06:44:21 +07:00
__init__.py litex_boards: Remove short imports since not really longer useful and mess up Python imports. 2022-05-03 17:53:57 +02:00