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litex-boards
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eca9bf10ae
litex-boards
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litex_boards
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partner
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Florent Kermarrec
f9619c4a8f
aller/tagus/nereid: use crossover UART, rename SoC to PCIe SoC and pass soc_sdram_argdict to PCIeSoC
2020-01-16 10:51:35 +01:00
..
platforms
platforms: always use 1e9/clk_freq for default_clk_period
2020-01-09 19:28:50 +01:00
targets
aller/tagus/nereid: use crossover UART, rename SoC to PCIe SoC and pass soc_sdram_argdict to PCIeSoC
2020-01-16 10:51:35 +01:00
__init__.py
Turn litex_boards.partner into module
2019-07-01 19:36:34 +02:00