litex-boards/litex_boards
Dan Callaghan 74c2178150 lattice_crosslink_nx_evn: don't set MASTER_SPI_PORT=SERIAL
Setting MASTER_SPI_PORT=SERIAL causes the SPI flash pins to be reserved
for use by the sysCONFIG logic, and prevents user logic from assigning
them. This made it impossible to have a Litex design which accesses the
SPI flash on this board.

Remove the setting, so that we get the default behaviour which permits
user logic to assign these pins. In the unlikely event that someone
needs the pins to stay reserved for sysCONFIG after configuration (I'm
not sure why this would be needed) they could explicitly add this
command in their design.
2021-09-01 18:47:17 +10:00
..
platforms Merge pull request #258 from danc86/clnexevn-device-arg 2021-09-01 10:22:42 +02:00
prog Add target for LPDDR4 Test Board 2021-03-30 14:50:02 +02:00
targets lattice_crosslink_nx_evn: don't set MASTER_SPI_PORT=SERIAL 2021-09-01 18:47:17 +10:00
tools general: add SPDX License identifier to header and specify files are part of LiteX-Boards. 2020-08-23 15:00:17 +02:00
__init__.py beaglewire: Rename to quertyembedded_beaglewire. 2021-09-01 09:36:09 +02:00