litex/CHANGES

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[> 2020.XX, planned for July 2020
---------------------------------
[> Issues resolved
------------------
2020-05-04 03:59:01 -04:00
- Fix flush_cpu_icache on VexRiscv.
2020-06-23 06:49:36 -04:00
- Fix `.data` section placed in rom (#566)
[> Added Features
------------------
- Properly integrate Minerva CPU.
- Add nMigen dependency.
- Pluggable CPUs.
- BIOS history, autocomplete.
- Improve boards's programmers.
- Add Microwatt CPU support (with GHDL-Yosys-plugin support for FOSS toolchains).
- Speedup Memtest using an LFSR.
- Add LedChaser on boards.
2020-05-14 03:34:37 -04:00
- Improve WishboneBridge.
- Improve Diamond constraints.
- Use InterconnectPointToPoint when 1 master,1 slave and no address translation.
- Add CV32E40P CPU support (ex RI5CY).
- JTAG UART with uart_name=jtag_uart (validated on Spartan6, 7-Series, Ultrascale(+)).
- Add Symbiflow experimental support on Arty.
2020-07-22 17:10:26 -04:00
- Add SDCard (SPI and SD modes) boot from FAT/exFAT filesystems with FatFs.
2020-06-11 13:24:54 -04:00
- Simplify boot with boot.json configuration file.
2020-06-23 06:49:36 -04:00
- Revert to a single crt0 (avoid ctr/xip variants).
2020-07-22 17:10:26 -04:00
- Add otional DMA bus for Cache Coherency on CPU(s) with DMA/Cache Coherency interface.
- Add AXI-Lite bus standard support.
[> API changes/Deprecation
--------------------------
2020-05-14 03:34:37 -04:00
- Add --build --load arguments to targets.
- Deprecate soc.interconnect.wishbone.UpConverter (will be rewritten if useful).
- Deprecate soc.interconnect.wishbone.CSRBank (Does not seem to be used by anyone).
- Move soc.interconnect.wishbone2csr.WB2CSR to soc.interconnect.wishbone.Wishbone2CSR.
- Move soc.interconnect.wishbonebridge.WishboneStreamingBridge to soc.cores.uart.Stream2Wishbone.
- Rename --gateware-toolchain target parameter to --toolchain.
[> 2020.04, released April 28th, 2020
-------------------------------------
[> Description
--------------
First release of LiteX and the ecosystem of cores!
LiteX is a Migen/MiSoC based Core/SoC builder that provides the infrastructure to easily create
Cores/SoCs (with or without CPU).
The common components of a SoC are provided directly:
- Buses and Streams (Wishbone, AXI, Avalon-ST)
- Interconnect
- Common cores (RAM, ROM, Timer, UART, etc...)
- CPU wrappers/integration
- etc...
And SoC creation capabilities can be greatly extended with the ecosystem of LiteX cores (DRAM,
PCIe, Ethernet, SATA, etc...) that can be integrated/simulated/build easily with LiteX.
It also provides build backends for open-source and vendors toolchains.
[> Issues resolved
------------------
- NA
[> Added Features
------------------
- NA
[> API changes/Deprecation
--------------------------
- https://github.com/enjoy-digital/litex/pull/399: Converting LiteX to use Python modules.