2020-05-01 13:07:43 -04:00
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[> 2020.XX, planned for July 2020
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---------------------------------
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[> Issues resolved
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------------------
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2020-05-04 03:59:01 -04:00
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- Fix flush_cpu_icache on VexRiscv.
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2020-06-23 06:49:36 -04:00
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- Fix `.data` section placed in rom (#566)
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2020-05-01 13:07:43 -04:00
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[> Added Features
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------------------
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2020-06-02 09:05:46 -04:00
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- Properly integrate Minerva CPU.
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- Add nMigen dependency.
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- Pluggable CPUs.
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- BIOS history, autocomplete.
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- Improve boards's programmers.
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- Add Microwatt CPU support (with GHDL-Yosys-plugin support for FOSS toolchains).
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- Speedup Memtest using an LFSR.
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- Add LedChaser on boards.
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2020-05-14 03:34:37 -04:00
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- Improve WishboneBridge.
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- Improve Diamond constraints.
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2020-06-02 09:05:46 -04:00
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- Use InterconnectPointToPoint when 1 master,1 slave and no address translation.
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- Add CV32E40P CPU support (ex RI5CY).
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- JTAG UART with uart_name=jtag_uart (validated on Spartan6, 7-Series, Ultrascale(+)).
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- Add Symbiflow experimental support on Arty.
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2020-07-22 17:10:26 -04:00
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- Add SDCard (SPI and SD modes) boot from FAT/exFAT filesystems with FatFs.
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2020-06-11 13:24:54 -04:00
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- Simplify boot with boot.json configuration file.
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2020-06-23 06:49:36 -04:00
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- Revert to a single crt0 (avoid ctr/xip variants).
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2020-07-22 17:10:26 -04:00
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- Add otional DMA bus for Cache Coherency on CPU(s) with DMA/Cache Coherency interface.
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- Add AXI-Lite bus standard support.
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2020-05-01 13:07:43 -04:00
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[> API changes/Deprecation
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--------------------------
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2020-05-14 03:34:37 -04:00
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- Add --build --load arguments to targets.
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2020-05-27 12:45:07 -04:00
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- Deprecate soc.interconnect.wishbone.UpConverter (will be rewritten if useful).
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- Deprecate soc.interconnect.wishbone.CSRBank (Does not seem to be used by anyone).
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- Move soc.interconnect.wishbone2csr.WB2CSR to soc.interconnect.wishbone.Wishbone2CSR.
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- Move soc.interconnect.wishbonebridge.WishboneStreamingBridge to soc.cores.uart.Stream2Wishbone.
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2020-06-02 09:05:46 -04:00
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- Rename --gateware-toolchain target parameter to --toolchain.
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2020-05-01 13:07:43 -04:00
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2020-04-28 05:36:44 -04:00
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[> 2020.04, released April 28th, 2020
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-------------------------------------
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[> Description
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--------------
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First release of LiteX and the ecosystem of cores!
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LiteX is a Migen/MiSoC based Core/SoC builder that provides the infrastructure to easily create
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Cores/SoCs (with or without CPU).
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The common components of a SoC are provided directly:
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- Buses and Streams (Wishbone, AXI, Avalon-ST)
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- Interconnect
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- Common cores (RAM, ROM, Timer, UART, etc...)
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- CPU wrappers/integration
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- etc...
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And SoC creation capabilities can be greatly extended with the ecosystem of LiteX cores (DRAM,
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PCIe, Ethernet, SATA, etc...) that can be integrated/simulated/build easily with LiteX.
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It also provides build backends for open-source and vendors toolchains.
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[> Issues resolved
|
|
|
|
|
------------------
|
|
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- NA
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|
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|
|
|
|
|
[> Added Features
|
|
|
|
|
------------------
|
|
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|
|
- NA
|
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|
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|
[> API changes/Deprecation
|
|
|
|
|
--------------------------
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- https://github.com/enjoy-digital/litex/pull/399: Converting LiteX to use Python modules.
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