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create first release, add CHANGES and note about Python modules in README.

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Florent Kermarrec 2020-04-28 11:36:44 +02:00
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[> 2020.04, released April 28th, 2020
-------------------------------------
[> Description
--------------
First release of LiteX and the ecosystem of cores!
LiteX is a Migen/MiSoC based Core/SoC builder that provides the infrastructure to easily create
Cores/SoCs (with or without CPU).
The common components of a SoC are provided directly:
- Buses and Streams (Wishbone, AXI, Avalon-ST)
- Interconnect
- Common cores (RAM, ROM, Timer, UART, etc...)
- CPU wrappers/integration
- etc...
And SoC creation capabilities can be greatly extended with the ecosystem of LiteX cores (DRAM,
PCIe, Ethernet, SATA, etc...) that can be integrated/simulated/build easily with LiteX.
It also provides build backends for open-source and vendors toolchains.
[> Issues resolved
------------------
- NA
[> Added Features
------------------
- NA
[> API changes/Deprecation
--------------------------
- https://github.com/enjoy-digital/litex/pull/399: Converting LiteX to use Python modules.

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```
[![](https://travis-ci.com/enjoy-digital/litex.svg?branch=master)](https://travis-ci.com/enjoy-digital/litex)
![License](https://img.shields.io/badge/License-BSD%202--Clause-orange.svg)
> **Note:** In release 2020.04, LiteX switched to Python modules instead of Git submodules. Existing users will have to reinstall LiteX following the [installation guide](https://github.com/enjoy-digital/litex/wiki/Installation#litex-installation-guide).
# Welcome to LiteX!
LiteX is a Migen/MiSoC based Core/SoC builder that provides the infrastructure to easily create Cores/SoCs (with or without CPU).
The common components of a SoC are provided directly: Buses and Streams (Wishbone, AXI, Avalon-ST), Interconnect, Common cores (RAM, ROM, Timer, UART, etc...), CPU wrappers/integration, etc... and SoC creation capabilities can be greatly extended with the ecosystem of LiteX cores (DRAM, PCIe, Ethernet, SATA, etc...) than can be integrated/simulated/build easily with LiteX. It also provides build backends for open-source and vendors toolchains.
The common components of a SoC are provided directly: Buses and Streams (Wishbone, AXI, Avalon-ST), Interconnect, Common cores (RAM, ROM, Timer, UART, etc...), CPU wrappers/integration, etc... and SoC creation capabilities can be greatly extended with the ecosystem of LiteX cores (DRAM, PCIe, Ethernet, SATA, etc...) that can be integrated/simulated/build easily with LiteX. It also provides build backends for open-source and vendors toolchains.
Think of Migen as a toolbox to create FPGA designs in Python and LiteX as a
SoC builder to create/develop/debug FPGA SoCs in Python.