litex/lib/sata/test/bist_tb.py

import random, copy

from migen.fhdl.std import *
from migen.genlib.record import *
from migen.sim.generic import run_simulation

from lib.sata.common import *
from lib.sata import SATACON
from lib.sata.bist import SATABIST

from lib.sata.test.hdd import *
from lib.sata.test.common import *

class TB(Module):
	def __init__(self):
		self.submodules.hdd = HDD(
				link_debug=False, link_random_level=0,
				transport_debug=False, transport_loopback=False,
				hdd_debug=True)
		self.submodules.controller = SATACON(self.hdd.phy)
		self.submodules.bist = SATABIST(max_count=2)
		self.comb += [
			self.bist.source.connect(self.controller.sink),
			self.controller.source.connect(self.bist.sink)
		]

	def gen_simulation(self, selfp):
		hdd = self.hdd
		hdd.malloc(0, 64)
		while True:
			selfp.bist.start = 1
			yield
			selfp.bist.start = 0
			yield
			while selfp.bist.done == 0:
				yield
			print("ctrl_errors: {} / data_errors {}".format(selfp.bist.ctrl_errors, selfp.bist.data_errors))
			selfp.bist.sector += 1

if __name__ == "__main__":
	run_simulation(TB(), ncycles=4096, vcd_name="my.vcd", keep_files=True)