42 lines
1.1 KiB
Python
42 lines
1.1 KiB
Python
import random, copy
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from migen.fhdl.std import *
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from migen.genlib.record import *
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from migen.sim.generic import run_simulation
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from lib.sata.common import *
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from lib.sata import SATACON
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from lib.sata.bist import SATABIST
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from lib.sata.test.hdd import *
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from lib.sata.test.common import *
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class TB(Module):
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def __init__(self):
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self.submodules.hdd = HDD(
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link_debug=False, link_random_level=0,
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transport_debug=False, transport_loopback=False,
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hdd_debug=True)
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self.submodules.controller = SATACON(self.hdd.phy)
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self.submodules.bist = SATABIST(max_count=2)
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self.comb += [
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self.bist.source.connect(self.controller.sink),
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self.controller.source.connect(self.bist.sink)
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]
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def gen_simulation(self, selfp):
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hdd = self.hdd
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hdd.malloc(0, 64)
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while True:
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selfp.bist.start = 1
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yield
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selfp.bist.start = 0
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yield
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while selfp.bist.done == 0:
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yield
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print("ctrl_errors: {} / data_errors {}".format(selfp.bist.ctrl_errors, selfp.bist.data_errors))
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selfp.bist.sector += 1
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if __name__ == "__main__":
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run_simulation(TB(), ncycles=4096, vcd_name="my.vcd", keep_files=True)
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