45 lines
1008 B
Python
45 lines
1008 B
Python
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import os
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import top
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# list Verilog sources before changing directory
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verilog_sources = []
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def add_core_dir(d):
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root = os.path.join("verilog", d, "rtl")
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files = os.listdir(root)
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for f in files:
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if f[-2:] == ".v":
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verilog_sources.append(os.path.join(root, f))
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def add_core_files(d, files):
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for f in files:
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verilog_sources.append(os.path.join("verilog", d, f))
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def get_qsf_prj():
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r = ""
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for s in verilog_sources:
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r += "set_global_assignment -name VERILOG_FILE " + s + "\n"
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return r
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add_core_dir("generic")
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add_core_dir("lm32")
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add_core_dir("hpdmc_sdr16")
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add_core_dir("fmlbrg")
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add_core_dir("uart")
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add_core_dir("rc5")
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add_core_dir("gpio")
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add_core_dir("spi_master")
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os.chdir("build")
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def str2file(filename, contents):
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f = open(filename, "w")
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f.write(contents)
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f.close()
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# generate top
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(src_verilog, qsf_cst) = top.get()
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str2file("soc.v", src_verilog)
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verilog_sources.append("build/soc.v")
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# generate Quartus project file
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qsf_prj = get_qsf_prj()
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str2file("soc.qsf", qsf_prj + qsf_cst)
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