Initialize de0_nano example
This commit is contained in:
Florent Kermarrec
parent
b8eaf0906a
commit
1578c74895
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PYTHON=
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all: build/soc.map
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# We need to change to the build directory because the Quartus tools
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# tend to dump a mess of various files in the current directory.
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build/soc.qsf:
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$(PYTHON) build.py
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build/soc.map: build/soc.qsf
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cp soc.qpf build/soc.qpf
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cd build && quartus_map soc.qpf
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clean:
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rm -rf build/*
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.PHONY: load clean
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import os
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import top
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# list Verilog sources before changing directory
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verilog_sources = []
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def add_core_dir(d):
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root = os.path.join("verilog", d, "rtl")
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files = os.listdir(root)
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for f in files:
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if f[-2:] == ".v":
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verilog_sources.append(os.path.join(root, f))
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def add_core_files(d, files):
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for f in files:
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verilog_sources.append(os.path.join("verilog", d, f))
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def get_qsf_prj():
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r = ""
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for s in verilog_sources:
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r += "set_global_assignment -name VERILOG_FILE " + s + "\n"
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return r
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add_core_dir("generic")
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add_core_dir("lm32")
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add_core_dir("hpdmc_sdr16")
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add_core_dir("fmlbrg")
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add_core_dir("uart")
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add_core_dir("rc5")
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add_core_dir("gpio")
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add_core_dir("spi_master")
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os.chdir("build")
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def str2file(filename, contents):
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f = open(filename, "w")
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f.write(contents)
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f.close()
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# generate top
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(src_verilog, qsf_cst) = top.get()
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str2file("soc.v", src_verilog)
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verilog_sources.append("build/soc.v")
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# generate Quartus project file
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qsf_prj = get_qsf_prj()
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str2file("soc.qsf", qsf_prj + qsf_cst)
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class Constraints:
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def __init__(self, uart0, rc50, gpio0, led0, sw0, spi_master0, hpdmc0):
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self.constraints = []
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def add(signal, pin, vec=-1, iostandard="3.3-V LVTTL", extra="", sch=""):
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self.constraints.append((signal, vec, pin, iostandard, extra,sch))
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def add_vec(signal, pins, iostandard="3.3-V LVTTL", extra="", sch=""):
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assert(signal.bv.width == len(pins)), "%s size : %d / qsf size : %d" %(signal,signal.bv.width,len(pins))
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i = 0
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for p in pins:
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add(signal, p, i, iostandard, extra)
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i += 1
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# uart0
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#add(uart0.tx, "TBD")
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#add(uart0.rx, "TBD")
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# rc50
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#add(rc50.rx, "TBD")
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# gpio0
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#add_vec(gpio0.inputs, ["TBD","TBD","TBD","TBD",
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# "TBD","TBD","TBD","TBD"])
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#add_vec(gpio0.outputs, ["TBD","TBD","TBD","TBD",
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# "TBD","TBD","TBD","TBD"])
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# led0
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add_vec(led0.outputs, ["A15", "A13", "B13", "A11",
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"D1" , "F3" , "B1" , "L3"])
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# sw0
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add_vec(sw0.inputs, ["M1", "T8", "B9", "M15"])
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# spi_master0
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add(spi_master0.cs, "TBD")
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add(spi_master0.sck, "TBD")
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add(spi_master0.mosi, "TBD")
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add(spi_master0.miso, "TBD")
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# hpdmc0
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add(hpdmc0.sdram_clk, "R4")
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add(hpdmc0.sdram_cke, "L7")
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add(hpdmc0.sdram_cs_n, "P6")
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add(hpdmc0.sdram_we_n, "C2")
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add(hpdmc0.sdram_cas_n, "L1")
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add(hpdmc0.sdram_ras_n, "L2")
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add_vec(hpdmc0.sdram_addr, ["P2","N5","N6","M8",
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"P8","T7","N8","T6",
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"R1","P1","N2","N1",
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"L4",])
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add_vec(hpdmc0.sdram_ba, ["M7","M6"])
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add_vec(hpdmc0.sdram_dqm, ["R6","T5"])
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add_vec(hpdmc0.sdram_dq, ["G2", "G1", "L8", "K5",
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"K2", "J2", "J1", "R7",
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"T4", "T2", "T3", "R3",
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"R5", "P3", "N3", "K1"])
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def get_ios(self):
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return set([c[0] for c in self.constraints])
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def get_qsf(self, ns):
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r = ""
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for c in self.constraints:
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r += "set_location_assignment PIN_"+str(c[2])
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r += " -to " + ns.get_name(c[0])
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if c[1] >= 0:
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r += "[" + str(c[1]) + "]"
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r += "\n"
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r += "set_instance_assignment -name IO_STANDARD "
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r += "\"" + c[3] + "\""
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r += " -to " + ns.get_name(c[0])
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if c[1] >= 0:
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r += "[" + str(c[1]) + "]"
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r += "\n"
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r += """
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set_global_assignment -name FAMILY "Cyclone IV E"
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set_global_assignment -name DEVICE EP4CE22F17C6
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set_global_assignment -name TOP_LEVEL_ENTITY "soc"
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set_global_assignment -name DEVICE_FILTER_PACKAGE FPGA
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set_global_assignment -name DEVICE_FILTER_PIN_COUNT 256
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set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 6
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set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
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set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO"
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set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO"
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set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"
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set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO"
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"""
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return r
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# -------------------------------------------------------------------------- #
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#
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# Copyright (C) 1991-2009 Altera Corporation
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# Your use of Altera Corporation's design tools, logic functions
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# and other software and tools, and its AMPP partner logic
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# functions, and any output files from any of the foregoing
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# (including device programming or simulation files), and any
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# associated documentation or information are expressly subject
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# to the terms and conditions of the Altera Program License
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# Subscription Agreement, Altera MegaCore Function License
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# Agreement, or other applicable license agreement, including,
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# without limitation, that your use is for the sole purpose of
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# programming logic devices manufactured by Altera and sold by
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# Altera or its authorized distributors. Please refer to the
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# applicable agreement for further details.
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#
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# -------------------------------------------------------------------------- #
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#
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# Quartus II
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# Version 9.0 Build 132 02/25/2009 SJ Full Version
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# Date created = 11:09:38 March 18, 2009
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#
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# -------------------------------------------------------------------------- #
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QUARTUS_VERSION = "9.0"
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DATE = "11:09:38 March 18, 2009"
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# Revisions
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PROJECT_REVISION = "soc"
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from math import ceil
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Hz = 1
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KHz = 10**3
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MHz = 10**6
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GHz = 10**9
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s = 1
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ms = 1/KHz
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us = 1/MHz
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ns = 1/GHz
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class t2n:
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def __init__(self, clk_period_ns):
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self.clk_period_ns = clk_period_ns
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self.clk_period_us = clk_period_ns*(GHz/MHz)
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self.clk_period_ms = clk_period_ns*(GHz/KHz)
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def ns(self,t,margin=True):
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if margin:
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t += self.clk_period_ns/2
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return ceil(t/self.clk_period_ns)
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def us(self,t,margin=True):
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if margin:
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t += self.clk_period_us/2
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return ceil(t/self.clk_period_us)
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def ms(self,t,margin=True):
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if margin:
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t += self.clk_period_ms/2
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return ceil(t/self.clk_period_ms)
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# De0Nano-System On Chip / Generic Base for a Custom SOC
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# - Lm32 SoftCore
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# - 32MB Sdram
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# - 2KB Eeprom (TBD)
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# - G Sensor & AD Converter (TBD)
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# - Up to 72 GPIO (8 in/ 8 out)
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# - Uart
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# - Spi Slave & Master (Only Master)
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#==============================================================================
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# I M P O R T
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#==============================================================================
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from fractions import Fraction
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from math import ceil
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from migen.fhdl.structure import *
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from migen.fhdl import verilog, autofragment
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from migen.bus import wishbone, csr, wishbone2csr, fml
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from soc import lm32, uart, rc5, gpio, spi_master, identifier, fmlbrg, hpdmc_sdr16
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from cmacros import get_macros
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from timings import *
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from constraints import Constraints
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#==============================================================================
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# P A R A M E T E R S
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#==============================================================================
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#Timings Param
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clk_freq = 50*MHz
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clk_period_ns = clk_freq*ns
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n = t2n(clk_period_ns)
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#==============================================================================
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# S O C
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#==============================================================================
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#
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# Configuration
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#===============================================================================
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# Csr
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csr_macros = get_macros("common/csrbase.h")
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def csr_offset(name):
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base = int(csr_macros[name + "_BASE"], 0)
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assert((base >= 0xe0000000) and (base <= 0xe0010000))
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return (base - 0xe0000000)//0x800
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# Interrupt
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interrupt_macros = get_macros("common/interrupt.h")
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def interrupt_n(name):
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return int(interrupt_macros[name + "_INTERRUPT"], 0)
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# Version
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version = get_macros("common/version.h")["VERSION"][1:-1]
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def get():
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#
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# Wishbone
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#===============================================================================
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cpu0 = lm32.LM32()
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wishbone2csr0 = wishbone2csr.WB2CSR()
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fmlbrg0 = fmlbrg.FMLBRG(16)
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hpdmc0 = hpdmc_sdr16.HPDMC_SDR16(13)
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# CSR 0x00000000 (shadow @0x80000000)
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# FML bridge 0x10000000 (shadow @0x90000000)
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wishbonecon = wishbone.InterconnectShared(
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[
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cpu0.ibus,
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cpu0.dbus
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], [
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(binc("000") , wishbone2csr0.wishbone),
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(binc("001") , fmlbrg0.wishbone)
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],
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register=True,
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offset=1)
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#
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# Fml
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#===============================================================================
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fmlcon0 = fml.Interconnect(fmlbrg0.fml,hpdmc0.fml)
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#
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# Csr
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#===============================================================================
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uart0 = uart.UART(csr_offset("UART"), clk_freq, baud=115200)
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identifier0 = identifier.Identifier(csr_offset("ID"), 0x1234, version, int(clk_freq))
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rc50 = rc5.RC5(csr_offset("RC5"),clk_freq)
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gpio0 = gpio.GPIO(csr_offset("GPIO"))
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led0 = gpio.GPIO(csr_offset("LED"))
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sw0 = gpio.GPIO(csr_offset("SW"),4)
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spi_master0 = spi_master.SPI_MASTER(csr_offset("SPI_MASTER"))
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csrcon0 = csr.Interconnect(wishbone2csr0.csr, [
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uart0.csr,
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identifier0.bank.interface,
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rc50.csr,
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gpio0.csr,
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led0.csr,
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sw0.csr,
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spi_master0.csr,
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hpdmc0.csr
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])
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#
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# Interrupts
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#===============================================================================
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interrupts = Fragment([
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cpu0.interrupt[interrupt_n("UART")].eq(uart0.irq),
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cpu0.interrupt[interrupt_n("RC5")].eq(rc50.irq),
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cpu0.interrupt[interrupt_n("GPIO")].eq(gpio0.irq)
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])
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#
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# HouseKeeping
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#===============================================================================
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frag = autofragment.from_local() + interrupts
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cst = Constraints(uart0, rc50, gpio0, led0, sw0, spi_master0, hpdmc0)
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src_verilog, vns = verilog.convert(frag,
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cst.get_ios(),
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name="soc",
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return_ns=True)
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src_qsf = cst.get_qsf(vns)
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return (src_verilog, src_qsf)
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