90 lines
2.8 KiB
Python
90 lines
2.8 KiB
Python
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class Constraints:
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def __init__(self, uart0, rc50, gpio0, led0, sw0, spi_master0, hpdmc0):
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self.constraints = []
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def add(signal, pin, vec=-1, iostandard="3.3-V LVTTL", extra="", sch=""):
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self.constraints.append((signal, vec, pin, iostandard, extra,sch))
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def add_vec(signal, pins, iostandard="3.3-V LVTTL", extra="", sch=""):
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assert(signal.bv.width == len(pins)), "%s size : %d / qsf size : %d" %(signal,signal.bv.width,len(pins))
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i = 0
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for p in pins:
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add(signal, p, i, iostandard, extra)
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i += 1
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# uart0
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#add(uart0.tx, "TBD")
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#add(uart0.rx, "TBD")
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# rc50
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#add(rc50.rx, "TBD")
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# gpio0
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#add_vec(gpio0.inputs, ["TBD","TBD","TBD","TBD",
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# "TBD","TBD","TBD","TBD"])
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#add_vec(gpio0.outputs, ["TBD","TBD","TBD","TBD",
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# "TBD","TBD","TBD","TBD"])
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# led0
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add_vec(led0.outputs, ["A15", "A13", "B13", "A11",
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"D1" , "F3" , "B1" , "L3"])
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# sw0
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add_vec(sw0.inputs, ["M1", "T8", "B9", "M15"])
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# spi_master0
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add(spi_master0.cs, "TBD")
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add(spi_master0.sck, "TBD")
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add(spi_master0.mosi, "TBD")
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add(spi_master0.miso, "TBD")
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# hpdmc0
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add(hpdmc0.sdram_clk, "R4")
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add(hpdmc0.sdram_cke, "L7")
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add(hpdmc0.sdram_cs_n, "P6")
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add(hpdmc0.sdram_we_n, "C2")
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add(hpdmc0.sdram_cas_n, "L1")
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add(hpdmc0.sdram_ras_n, "L2")
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add_vec(hpdmc0.sdram_addr, ["P2","N5","N6","M8",
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"P8","T7","N8","T6",
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"R1","P1","N2","N1",
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"L4",])
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add_vec(hpdmc0.sdram_ba, ["M7","M6"])
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add_vec(hpdmc0.sdram_dqm, ["R6","T5"])
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add_vec(hpdmc0.sdram_dq, ["G2", "G1", "L8", "K5",
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"K2", "J2", "J1", "R7",
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"T4", "T2", "T3", "R3",
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"R5", "P3", "N3", "K1"])
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def get_ios(self):
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return set([c[0] for c in self.constraints])
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def get_qsf(self, ns):
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r = ""
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for c in self.constraints:
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r += "set_location_assignment PIN_"+str(c[2])
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r += " -to " + ns.get_name(c[0])
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if c[1] >= 0:
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r += "[" + str(c[1]) + "]"
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r += "\n"
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r += "set_instance_assignment -name IO_STANDARD "
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r += "\"" + c[3] + "\""
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r += " -to " + ns.get_name(c[0])
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if c[1] >= 0:
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r += "[" + str(c[1]) + "]"
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r += "\n"
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r += """
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set_global_assignment -name FAMILY "Cyclone IV E"
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set_global_assignment -name DEVICE EP4CE22F17C6
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set_global_assignment -name TOP_LEVEL_ENTITY "soc"
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set_global_assignment -name DEVICE_FILTER_PACKAGE FPGA
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set_global_assignment -name DEVICE_FILTER_PIN_COUNT 256
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set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 6
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set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
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set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO"
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set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO"
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set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"
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set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO"
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"""
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return r
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