litex/README

149 lines
4.8 KiB
Plaintext
Raw Normal View History

__ _ __ ______ __
/ / (_) /____ / __/ /_/ /
/ /__/ / __/ -_) _// __/ _ \
/____/_/\__/\__/___/\__/_//_/
2015-01-27 17:46:15 -05:00
Copyright 2012-2015 / EnjoyDigital
florent@enjoy-digital.fr
A small footprint and configurable Ethernet core
2015-02-12 15:39:34 -05:00
with UDP/IP hw stack and Etherbone frontend
2015-01-27 17:46:15 -05:00
developed by EnjoyDigital
2015-02-09 17:05:59 -05:00
[> Doc
---------
HTML : www.enjoy-digital.fr/litex/liteeth/
PDF : www.enjoy-digital.fr/litex/liteeth.pdf
2015-01-27 17:46:15 -05:00
[> Intro
---------
LiteEth provides a small footprint and configurable Ethernet core.
2015-01-27 17:46:15 -05:00
LiteEth is part of LiteX libraries whose aims are to lower entry level of
2015-01-27 17:46:15 -05:00
complex FPGA IP cores by providing simple, elegant and efficient implementations
ofcomponents used in today's SoC such as Ethernet, SATA, PCIe, SDRAM Controller...
The core uses simple and specific streaming buses and will provides in the future
adapters to use standardized AXI or Avalon-ST streaming buses.
Since Python is used to describe the HDL, the core is highly and easily
configurable.
LiteEth uses technologies developed in partnership with M-Labs Ltd:
2015-01-27 17:46:15 -05:00
- Migen enables generating HDL with Python in an efficient way.
- MiSoC provides the basic blocks to build a powerful and small footprint SoC.
LiteEth can be used as a Migen/MiSoC library (by simply installing it
2015-01-27 17:46:15 -05:00
with the provided setup.py) or can be integrated with your standard design flow
by generating the verilog rtl that you will use as a standard core.
[> Features
-----------
- Ethernet MAC with various interfaces and various PHYs (GMII, MII, Loopback)
2015-02-09 17:05:59 -05:00
- Hardware UDP/IP stack with ARP and ICMP
2015-01-27 17:46:15 -05:00
2015-02-12 15:39:34 -05:00
[> Possible improvements
2015-01-27 17:46:15 -05:00
-------------------------
- add standardized interfaces (AXI, Avalon-ST)
- add DMA interface to MAC
2015-02-09 13:35:42 -05:00
- add RGMII/SGMII PHYs
2015-02-12 15:39:34 -05:00
- ... See below Support and consulting :)
2015-01-27 17:46:15 -05:00
If you want to support these features, please contact us at florent [AT]
enjoy-digital.fr. You can also contact our partner on the public mailing list
devel [AT] lists.m-labs.hk.
[> Getting started
------------------
2015-02-12 15:39:34 -05:00
1. Install Python3 and your vendor's software
2015-02-09 13:35:42 -05:00
2015-02-12 15:39:34 -05:00
2. Obtain Migen and install it:
git clone https://github.com/m-labs/migen
2015-02-09 13:35:42 -05:00
cd migen
python3 setup.py install
cd ..
2015-02-12 15:39:34 -05:00
3. Obtain MiSoC and install it:
git clone https://github.com/m-labs/misoc --recursive
cd misoc
python3 setup.py install
cd ..
Note: in case you have issues with Migen/MiSoC, please retry
with our forks at:
https://github.com/enjoy-digital/misoc
https://github.com/enjoy-digital/migen
until new features are merged.
4. Obtain LiteScope and install it:
2015-02-09 13:35:42 -05:00
git clone https://github.com/enjoy-digital/litescope
cd litescope
python3 setup.py install
cd ..
5. Obtain LiteEth
git clone https://github.com/enjoy-digital/liteeth
6. Build and load UDP loopback design (only for KC705 for now):
python3 make.py all (-s UDPSoCDevel to add LiteScopeLA)
7. Test design (only for KC705 for now):
2015-02-12 15:39:34 -05:00
try to ping 192.168.1.40
go to ./test directory:
2015-02-09 13:35:42 -05:00
change com port in config.py to your com port
2015-02-12 15:39:34 -05:00
run make test_udp
8. Build and load Etherbone design (only for KC705 for now):
python3 make.py -t Etherbone
9. Test design (only for KC705 for now):
2015-02-09 13:35:42 -05:00
try to ping 192.168.1.40
2015-02-12 15:39:34 -05:00
go to ./test directory run:
run make test_etherbone
2015-01-27 17:46:15 -05:00
[> Simulations:
2015-02-09 13:35:42 -05:00
Simulations are available in ./liteth/test/:
- mac_core_tb
- mac_wishbone_tb
- arp_tb
- ip_tb
- icmp_tb
- udp_tb
All ethernet layers have their own model tested against real Ethernet dumps (dumps.py)
To run a simulation, move to ./liteeth/test and run:
make simulation_name
2015-01-27 17:46:15 -05:00
[> Tests :
2015-02-12 15:39:34 -05:00
An UDP loopback example is provided and be controlled with: ./test/test_udp.py
An Etherbone example with Wishbone SRAM is provided and can be controlled with:
./test/test_etherbone.py
2015-01-27 17:46:15 -05:00
[> License
-----------
LiteEth is released under the very permissive two-clause BSD license. Under
the terms of this license, you are authorized to use LiteEth for closed-source
2015-01-27 17:46:15 -05:00
proprietary designs.
Even though we do not require you to do so, those things are awesome, so please
do them if possible:
- tell us that you are using LiteEth
- cite LiteEth in publications related to research it has helped
2015-01-27 17:46:15 -05:00
- send us feedback and suggestions for improvements
- send us bug reports when something goes wrong
- send us the modifications and improvements you have done to LiteEth.
2015-01-27 17:46:15 -05:00
2015-02-12 15:39:34 -05:00
[> Support and consulting
2015-01-27 17:46:15 -05:00
--------------------------
We love open-source hardware and like sharing our designs with others.
LiteEth is developed and maintained by EnjoyDigital.
2015-01-27 17:46:15 -05:00
If you would like to know more about LiteEth or if you are already a happy
2015-01-27 17:46:15 -05:00
user and would like to extend it for your needs, EnjoyDigital can provide standard
commercial support as well as consulting services.
So feel free to contact us, we'd love to work with you! (and eventually shorten
the list of the possible improvements :)
[> Contact
E-mail: florent [AT] enjoy-digital.fr