change name to LiteEth (LiteEthernet is too long...)

LICENSE

@@ -1,4 +1,4 @@
-Unless otherwise noted, LiteScope is copyright (C) 2015 Florent Kermarrec.
+Unless otherwise noted, LiteEth is copyright (C) 2015 Florent Kermarrec.
 
 Redistribution and use in source and binary forms, with or without modification,
 are permitted provided that the following conditions are met:

README

@@ -1,7 +1,7 @@
-          __   _ __      ______  __                    __
-         / /  (_) /____ / __/ /_/ /  ___ _______  ___ / /_
-        / /__/ / __/ -_) _// __/ _ \/ -_) __/ _ \/ -_) __/
-       /____/_/\__/\__/___/\__/_//_/\__/_/ /_//_/\__/\__/
+                __   _ __      ______  __
+               / /  (_) /____ / __/ /_/ /
+              / /__/ / __/ -_) _// __/ _ \
+             /____/_/\__/\__/___/\__/_//_/
 
            Copyright 2012-2015 / EnjoyDigital
                 florent@enjoy-digital.fr
@@ -11,9 +11,9 @@
 
 [> Intro
 ---------
-LiteEthernet provides a small footprint and configurable Ethernet core.
+LiteEth provides a small footprint and configurable Ethernet core.
 
-LiteEthernet is part of LiteX libraries whose aims are to lower entry level of
+LiteEth is part of LiteX libraries whose aims are to lower entry level of
 complex FPGA IP cores by providing simple, elegant and efficient implementations
 ofcomponents used in today's SoC such as Ethernet, SATA, PCIe, SDRAM Controller...
 
@@ -23,11 +23,11 @@ adapters to use standardized AXI or Avalon-ST streaming buses.
 Since Python is used to describe the HDL, the core is highly and easily
 configurable.
 
-LiteEthernet uses technologies developed in partnership with M-Labs Ltd:
+LiteEth uses technologies developed in partnership with M-Labs Ltd:
  - Migen enables generating HDL with Python in an efficient way.
  - MiSoC provides the basic blocks to build a powerful and small footprint SoC.
 
-LiteEthernet can be used as a Migen/MiSoC library (by simply installing  it
+LiteEth can be used as a Migen/MiSoC library (by simply installing  it
 with the provided setup.py) or can be integrated with your standard design flow
 by generating the verilog rtl that you will use as a standard core.
 
@@ -62,24 +62,24 @@ devel [AT] lists.m-labs.hk.
 
 [> License
 -----------
-LiteEthernet is released under the very permissive two-clause BSD license. Under
-the terms of this license, you are authorized to use LiteEthernet for closed-source
+LiteEth is released under the very permissive two-clause BSD license. Under
+the terms of this license, you are authorized to use LiteEth for closed-source
 proprietary designs.
 Even though we do not require you to do so, those things are awesome, so please
 do them if possible:
- - tell us that you are using LiteEthernet
- - cite LiteEthernet in publications related to research it has helped
+ - tell us that you are using LiteEth
+ - cite LiteEth in publications related to research it has helped
  - send us feedback and suggestions for improvements
  - send us bug reports when something goes wrong
- - send us the modifications and improvements you have done to LiteEthernet.
+ - send us the modifications and improvements you have done to LiteEth.
 
 [> Support and Consulting
 --------------------------
 We love open-source hardware and like sharing our designs with others.
 
-LiteEthernet is developed and maintained by EnjoyDigital.
+LiteEth is developed and maintained by EnjoyDigital.
 
-If you would like to know more about LiteEthernet or if you are already a happy
+If you would like to know more about LiteEth or if you are already a happy
 user and would like to extend it for your needs, EnjoyDigital can provide standard
 commercial support as well as consulting services.
 

setup.py

@@ -9,18 +9,18 @@ README = open(os.path.join(here, "README")).read()
 
 required_version = (3, 3)
 if sys.version_info < required_version:
-	raise SystemExit("LiteEthernet requires python {0} or greater".format(
+	raise SystemExit("LiteEth requires python {0} or greater".format(
 		".".join(map(str, required_version))))
 
 setup(
 	name="liteethernet",
 	version="unknown",
-	description="small footprint and configurable embedded FPGA logic analyzer",
+	description="small footprint and configurable Ethernet core",
 	long_description=README,
 	author="Florent Kermarrec",
 	author_email="florent@enjoy-digital.fr",
 	url="http://enjoy-digital.fr",
-	download_url="https://github.com/enjoy-digital/liteethernet",
+	download_url="https://github.com/enjoy-digital/liteeth",
 	packages=find_packages(here),
 	license="GPL",
 	platforms=["Any"],