2011-12-16 15:30:14 -05:00
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from migen.fhdl.structure import *
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2011-12-16 10:02:55 -05:00
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from migen.bus.csr import *
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from migen.bank.description import *
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2011-12-05 11:43:56 -05:00
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class Bank:
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def __init__(self, description, address=0):
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self.description = description
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self.address = address
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self.interface = Slave()
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2011-12-16 10:02:55 -05:00
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def get_fragment(self):
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2011-12-05 11:43:56 -05:00
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comb = []
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sync = []
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2011-12-18 15:47:48 -05:00
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sel = Signal()
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comb.append(sel.eq(self.interface.a_i[9:] == Constant(self.address, BV(5))))
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2011-12-05 11:43:56 -05:00
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2012-02-06 05:18:30 -05:00
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nbits = bits_for(len(self.description)-1)
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2011-12-05 11:43:56 -05:00
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# Bus writes
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bwcases = []
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2012-02-06 05:18:30 -05:00
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for i, reg in enumerate(self.description):
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2011-12-17 18:28:04 -05:00
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if reg.raw is None:
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bwra = [Constant(i, BV(nbits))]
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2012-02-06 05:18:30 -05:00
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for j, field in enumerate(reg.fields):
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2011-12-17 18:28:04 -05:00
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if field.access_bus == WRITE_ONLY or field.access_bus == READ_WRITE:
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bwra.append(field.storage.eq(self.interface.d_i[j]))
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if len(bwra) > 1:
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bwcases.append(bwra)
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else:
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comb.append(reg.dev_r.eq(self.interface.d_i[:reg.raw.width]))
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2011-12-18 15:47:48 -05:00
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comb.append(reg.dev_re.eq(sel & \
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2011-12-17 18:28:04 -05:00
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self.interface.we_i & \
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(self.interface.a_i[:nbits] == Constant(i, BV(nbits)))))
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2011-12-05 11:43:56 -05:00
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if bwcases:
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2011-12-18 15:47:48 -05:00
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sync.append(If(sel & self.interface.we_i, Case(self.interface.a_i[:nbits], *bwcases)))
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2011-12-05 11:43:56 -05:00
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# Bus reads
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brcases = []
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2012-02-06 05:18:30 -05:00
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for i, reg in enumerate(self.description):
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2011-12-17 18:28:04 -05:00
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if reg.raw is None:
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brs = []
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reg_readable = False
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2012-02-06 05:18:30 -05:00
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for j, field in enumerate(reg.fields):
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2011-12-17 18:28:04 -05:00
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if field.access_bus == READ_ONLY or field.access_bus == READ_WRITE:
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brs.append(field.storage)
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reg_readable = True
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else:
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brs.append(Constant(0, BV(field.size)))
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if reg_readable:
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if len(brs) > 1:
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brcases.append([Constant(i, BV(nbits)), self.interface.d_o.eq(f.Cat(*brs))])
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else:
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brcases.append([Constant(i, BV(nbits)), self.interface.d_o.eq(brs[0])])
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else:
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brcases.append([Constant(i, BV(nbits)), self.interface.d_o.eq(reg.dev_w)])
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2011-12-05 11:43:56 -05:00
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if brcases:
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2011-12-17 09:54:49 -05:00
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sync.append(self.interface.d_o.eq(Constant(0, BV(8))))
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2011-12-18 15:47:48 -05:00
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sync.append(If(sel, Case(self.interface.a_i[:nbits], *brcases)))
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2011-12-05 11:43:56 -05:00
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else:
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2011-12-17 09:54:49 -05:00
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comb.append(self.interface.d_o.eq(Constant(0, BV(8))))
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2011-12-05 11:43:56 -05:00
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# Device access
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for reg in self.description:
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2011-12-17 18:28:04 -05:00
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if reg.raw is None:
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for field in reg.fields:
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if field.access_dev == READ_ONLY or field.access_dev == READ_WRITE:
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comb.append(field.dev_r.eq(field.storage))
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if field.access_dev == WRITE_ONLY or field.access_dev == READ_WRITE:
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sync.append(If(field.dev_we, field.storage.eq(field.dev_w)))
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2011-12-05 11:43:56 -05:00
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2011-12-16 15:30:14 -05:00
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return Fragment(comb, sync)
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