Hardware
/
litex
mirror of https://github.com/enjoy-digital/litex.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Pay a bit more attention to PEP8

This commit is contained in:
Sebastien Bourdeauducq 2011-12-16 16:02:55 +01:00
parent 929cc98070
commit 39b7190334
18 changed files with 107 additions and 105 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
examples/corelogic_conv.py
View File

@ -4,6 +4,6 @@ from migen.corelogic import roundrobin, divider
r = roundrobin.Inst(5)
d = divider.Inst(16)
frag = r.GetFragment() + d.GetFragment()
frag = r.get_fragment() + d.get_fragment()
o = verilog.Convert(frag, {r.request, r.grant, d.ready_o, d.quotient_o, d.remainder_o, d.start_i, d.dividend_i, d.divisor_i})
print(o)
print(o)

6
examples/lm32_inst.py
View File

@ -37,11 +37,11 @@ class LM32:
"rst_i",
"lm32")
def GetFragment(self):
def get_fragment(self):
return f.Fragment(instances=[self.inst])
cpus = [LM32() for i in range(4)]
frag = f.Fragment()
for cpu in cpus:
frag += cpu.GetFragment()
print(verilog.Convert(frag, set([cpus[0].inst.ins["interrupt"], cpus[0].inst.outs["I_WE_O"]])))
frag += cpu.get_fragment()
print(verilog.Convert(frag, set([cpus[0].inst.ins["interrupt"], cpus[0].inst.outs["I_WE_O"]])))

4
examples/simple_gpio.py
View File

@ -18,8 +18,8 @@ insync = [f.Assign(gpio_in_s, gpio_in), f.Assign(ifield.dev_w, gpio_in_s)]
inf = f.Fragment(incomb, insync)
bank = csrgen.Bank([oreg, ireg])
f = bank.GetFragment() + inf
f = bank.get_fragment() + inf
i = bank.interface
ofield.dev_r.name = "gpio_out"
v = verilog.Convert(f, {i.d_o, ofield.dev_r, i.a_i, i.we_i, i.d_i, gpio_in})
print(v)
print(v)

2
examples/wb_intercon/intercon_conv.py
View File

@ -12,7 +12,7 @@ wishbonecon0 = wishbone.InterconnectShared(
register=True,
offset=1)
frag = wishbonecon0.GetFragment()
frag = wishbonecon0.get_fragment()
v = verilog.Convert(frag, name="intercon", ios={m1.cyc_o, m1.stb_o, m1.we_o, m1.adr_o, m1.sel_o, m1.dat_o, m1.dat_i, m1.ack_i,
m2.cyc_o, m2.stb_o, m2.we_o, m2.adr_o, m2.sel_o, m2.dat_o, m2.dat_i, m2.ack_i,
s1.cyc_i, s1.stb_i, s1.we_i, s1.adr_i, s1.sel_i, s1.dat_i, s1.dat_o, s1.ack_o,

14
migen/bank/csrgen.py
View File

@ -1,17 +1,15 @@
from ..fhdl import structure as f
from ..bus.csr import *
from .description import *
from functools import partial
from migen.fhdl import structure as f
from migen.bus.csr import *
from migen.bank.description import *
class Bank:
def __init__(self, description, address=0):
self.description = description
self.address = address
self.interface = Slave()
d = partial(f.Declare, self)
d("_sel")
f.declare_signal(self, "_sel")
def GetFragment(self):
def get_fragment(self):
a = f.Assign
comb = []
sync = []
@ -19,7 +17,7 @@ class Bank:
comb.append(a(self._sel, self.interface.a_i[10:] == f.Constant(self.address, f.BV(4))))
nregs = len(self.description)
nbits = f.BitsFor(nregs-1)
nbits = f.bits_for(nregs-1)
# Bus writes
bwcases = []

6
migen/bank/description.py
View File

@ -1,11 +1,11 @@
from ..fhdl import structure as f
from migen.fhdl import structure as f
class Register:
def __init__(self, name):
self.name = name
self.fields = []
def AddField(self, f):
def add_field(self, f):
self.fields.append(f)
(READ_ONLY, WRITE_ONLY, READ_WRITE) = range(3)
@ -25,4 +25,4 @@ class Field:
if self.access_dev == WRITE_ONLY or self.access_dev == READ_WRITE:
self.dev_w = f.Signal(f.BV(self.size), fullname + "_w")
self.dev_we = f.Signal(name=fullname + "_we")
self.parent.AddField(self)
self.parent.add_field(self)

4
migen/bus/csr.py
View File

@ -1,5 +1,5 @@
from migen.fhdl import structure as f
from .simple import Simple
from migen.bus.simple import Simple
_desc = [
(True, "a", 14),
@ -21,7 +21,7 @@ class Interconnect:
self.master = master
self.slaves = slaves
def GetFragment(self):
def get_fragment(self):
a = f.Assign
comb = []
rb = f.Constant(0, f.BV(32))

4
migen/bus/simple.py
View File

@ -1,6 +1,6 @@
from migen.fhdl import structure as f
def GetSigName(signal, slave):
def get_sig_name(signal, slave):
if signal[0] ^ slave:
suffix = "_o"
else:
@ -18,5 +18,5 @@ class Simple():
busname = modules[len(modules)-1]
if name:
busname += "_" + name
signame = GetSigName(signal, slave)
signame = get_sig_name(signal, slave)
setattr(self, signame, f.Signal(f.BV(signal[2]), busname + "_" + signame))

27
migen/bus/wishbone.py
View File

@ -1,7 +1,8 @@
from functools import partial
from migen.fhdl import structure as f
from migen.corelogic import roundrobin, multimux
from .simple import Simple, GetSigName
from functools import partial
from migen.bus.simple import Simple, get_sig_name
_desc = [
(True, "adr", 32),
@ -31,17 +32,17 @@ class Arbiter:
self.target = target
self.rr = roundrobin.Inst(len(self.masters))
def GetFragment(self):
def get_fragment(self):
comb = []
# mux master->slave signals
m2s_names = [GetSigName(x, False) for x in _desc if x[0]]
m2s_names = [get_sig_name(x, False) for x in _desc if x[0]]
m2s_masters = [[getattr(m, name) for name in m2s_names] for m in self.masters]
m2s_target = [getattr(self.target, name) for name in m2s_names]
comb += multimux.MultiMux(self.rr.grant, m2s_masters, m2s_target)
comb += multimux.multimux(self.rr.grant, m2s_masters, m2s_target)
# connect slave->master signals
s2m_names = [GetSigName(x, False) for x in _desc if not x[0]]
s2m_names = [get_sig_name(x, False) for x in _desc if not x[0]]
for name in s2m_names:
source = getattr(self.target, name)
i = 0
@ -57,7 +58,7 @@ class Arbiter:
reqs = [m.cyc_o for m in self.masters]
comb.append(f.Assign(self.rr.request, f.Cat(*reqs)))
return f.Fragment(comb) + self.rr.GetFragment()
return f.Fragment(comb) + self.rr.get_fragment()
class Decoder:
# slaves is a list of pairs:
@ -75,7 +76,7 @@ class Decoder:
self.register = register
addresses = [slave[0] for slave in self.slaves]
maxbits = max([f.BitsFor(addr) for addr in addresses])
maxbits = max([f.bits_for(addr) for addr in addresses])
def mkconst(x):
if isinstance(x, int):
return f.Constant(x, f.BV(maxbits))
@ -84,11 +85,11 @@ class Decoder:
self.addresses = list(map(mkconst, addresses))
ns = len(self.slaves)
d = partial(f.Declare, self)
d = partial(f.declare_signal, self)
d("_slave_sel", f.BV(ns))
d("_slave_sel_r", f.BV(ns))
def GetFragment(self):
def get_fragment(self):
comb = []
sync = []
@ -105,7 +106,7 @@ class Decoder:
comb.append(f.Assign(self._slave_sel_r, self._slave_sel))
# connect master->slaves signals except cyc
m2s_names = [(GetSigName(x, False), GetSigName(x, True))
m2s_names = [(get_sig_name(x, False), get_sig_name(x, True))
for x in _desc if x[0] and x[1] != "cyc"]
comb += [f.Assign(getattr(slave[1], name[1]), getattr(self.master, name[0]))
for name in m2s_names for slave in self.slaves]
@ -142,5 +143,5 @@ class InterconnectShared:
self._decoder = Decoder(self._shared, slaves, offset, register)
self.addresses = self._decoder.addresses
def GetFragment(self):
return self._arbiter.GetFragment() + self._decoder.GetFragment()
def get_fragment(self):
return self._arbiter.get_fragment() + self._decoder.get_fragment()

8
migen/bus/wishbone2csr.py
View File

@ -1,7 +1,7 @@
from migen.bus import wishbone
from migen.bus import csr
from migen.fhdl import structure as f
from migen.corelogic import timeline
from . import wishbone
from . import csr
class Inst():
def __init__(self):
@ -12,11 +12,11 @@ class Inst():
(2, [f.Assign(self.wishbone.ack_o, 1)]),
(3, [f.Assign(self.wishbone.ack_o, 0)])])
def GetFragment(self):
def get_fragment(self):
sync = [
f.Assign(self.csr.we_o, 0),
f.Assign(self.csr.d_o, self.wishbone.dat_i),
f.Assign(self.csr.a_o, self.wishbone.adr_i[2:16]),
f.Assign(self.wishbone.dat_o, self.csr.d_i)
]
return f.Fragment(sync=sync) + self.timeline.GetFragment()
return f.Fragment(sync=sync) + self.timeline.get_fragment()

9
migen/corelogic/divider.py
View File

@ -1,11 +1,12 @@
from migen.fhdl import structure as f
from functools import partial
from migen.fhdl import structure as f
class Inst:
def __init__(self, w):
self.w = w
d = partial(f.Declare, self)
d = partial(f.declare_signal, self)
d("start_i")
d("dividend_i", f.BV(w))
@ -15,11 +16,11 @@ class Inst:
d("remainder_o", f.BV(w))
d("_qr", f.BV(2*w))
d("_counter", f.BV(f.BitsFor(w)))
d("_counter", f.BV(f.bits_for(w)))
d("_divisor_r", f.BV(w))
d("_diff", f.BV(w+1))
def GetFragment(self):
def get_fragment(self):
a = f.Assign
comb = [
a(self.quotient_o, self._qr[:self.w]),

4
migen/corelogic/multimux.py
View File

@ -1,6 +1,6 @@
from migen.fhdl import structure as f
def MultiMux(sel, inputs, output):
def multimux(sel, inputs, output):
n = len(inputs)
i = 0
comb = []
@ -10,4 +10,4 @@ def MultiMux(sel, inputs, output):
default = cases.pop()[1]
comb.append(f.Case(sel, cases, default))
i += 1
return comb
return comb

10
migen/corelogic/roundrobin.py
View File

@ -3,11 +3,11 @@ from migen.fhdl import structure as f
class Inst:
def __init__(self, n):
self.n = n
self.bn = f.BitsFor(self.n-1)
f.Declare(self, "request", f.BV(self.n))
f.Declare(self, "grant", f.BV(self.bn))
self.bn = f.bits_for(self.n-1)
f.declare_signal(self, "request", f.BV(self.n))
f.declare_signal(self, "grant", f.BV(self.bn))
def GetFragment(self):
def get_fragment(self):
cases = []
for i in range(self.n):
switch = []
@ -19,4 +19,4 @@ class Inst:
case = f.If(~self.request[i], switch)
cases.append((f.Constant(i, f.BV(self.bn)), case))
statement = f.Case(self.grant, cases)
return f.Fragment(sync=[statement])
return f.Fragment(sync=[statement])

8
migen/corelogic/timeline.py
View File

@ -5,9 +5,9 @@ class Inst:
self.trigger = trigger
self.events = events
self.lastevent = max([e[0] for e in events])
f.Declare(self, "_counter", f.BV(f.BitsFor(self.lastevent)))
f.declare_signal(self, "_counter", f.BV(f.bits_for(self.lastevent)))
def GetFragment(self):
def get_fragment(self):
counterlogic = f.If(self._counter != f.Constant(0, self._counter.bv),
[f.Assign(self._counter, self._counter + f.Constant(1, self._counter.bv))],
[f.If(self.trigger, [f.Assign(self._counter, f.Constant(1, self._counter.bv))])])
@ -17,11 +17,11 @@ class Inst:
counterlogic = f.If(self._counter == self.lastevent,
[f.Assign(self._counter, f.Constant(0, self._counter.bv))],
[counterlogic])
def getcond(e):
def get_cond(e):
if e[0] == 0:
return self.trigger & (self._counter == f.Constant(0, self._counter.bv))
else:
return self._counter == f.Constant(e[0], self._counter.bv)
sync = [f.If(getcond(e), e[1]) for e in self.events]
sync = [f.If(get_cond(e), e[1]) for e in self.events]
sync.append(counterlogic)
return f.Fragment(sync=sync)

9
migen/fhdl/autofragment.py
View File

@ -1,12 +1,13 @@
from .structure import *
import inspect
def FromLocal():
from migen.fhdl.structure import *
def from_local():
f = Fragment()
frame = inspect.currentframe().f_back
ns = frame.f_locals
for x in ns:
obj = ns[x]
if hasattr(obj, "GetFragment"):
f += obj.GetFragment()
if hasattr(obj, "get_fragment"):
f += obj.get_fragment()
return f

58
migen/fhdl/convtools.py
View File

@ -5,7 +5,7 @@ class Namespace:
self.counts = {}
self.sigs = {}
def GetName(self, sig):
def get_name(self, sig):
try:
n = self.sigs[sig]
if n:
@ -24,77 +24,77 @@ class Namespace:
else:
return sig.name
def ListSignals(node):
def list_signals(node):
if isinstance(node, Constant):
return set()
elif isinstance(node, Signal):
return {node}
elif isinstance(node, Operator):
l = list(map(ListSignals, node.operands))
l = list(map(list_signals, node.operands))
return set().union(*l)
elif isinstance(node, Slice):
return ListSignals(node.value)
return list_signals(node.value)
elif isinstance(node, Cat):
l = list(map(ListSignals, node.l))
l = list(map(list_signals, node.l))
return set().union(*l)
elif isinstance(node, Replicate):
return ListSignals(node.v)
return list_signals(node.v)
elif isinstance(node, Assign):
return ListSignals(node.l) | ListSignals(node.r)
return list_signals(node.l) | list_signals(node.r)
elif isinstance(node, StatementList):
l = list(map(ListSignals, node.l))
l = list(map(list_signals, node.l))
return set().union(*l)
elif isinstance(node, If):
return ListSignals(node.cond) | ListSignals(node.t) | ListSignals(node.f)
return list_signals(node.cond) | list_signals(node.t) | list_signals(node.f)
elif isinstance(node, Case):
l = list(map(lambda x: ListSignals(x[1]), node.cases))
return ListSignals(node.test).union(*l).union(ListSignals(node.default))
l = list(map(lambda x: list_signals(x[1]), node.cases))
return list_signals(node.test).union(*l).union(list_signals(node.default))
elif isinstance(node, Fragment):
return ListSignals(node.comb) | ListSignals(node.sync)
return list_signals(node.comb) | list_signals(node.sync)
else:
raise TypeError
def ListTargets(node):
def list_targets(node):
if isinstance(node, Signal):
return {node}
elif isinstance(node, Slice):
return ListTargets(node.value)
return list_targets(node.value)
elif isinstance(node, Cat):
l = list(map(ListTargets, node.l))
l = list(map(list_targets, node.l))
return set().union(*l)
elif isinstance(node, Replicate):
return ListTargets(node.v)
return list_targets(node.v)
elif isinstance(node, Assign):
return ListTargets(node.l)
return list_targets(node.l)
elif isinstance(node, StatementList):
l = list(map(ListTargets, node.l))
l = list(map(list_targets, node.l))
return set().union(*l)
elif isinstance(node, If):
return ListTargets(node.t) | ListTargets(node.f)
return list_targets(node.t) | list_targets(node.f)
elif isinstance(node, Case):
l = list(map(lambda x: ListTargets(x[1]), node.cases))
return ListTargets(node.default).union(*l)
l = list(map(lambda x: list_targets(x[1]), node.cases))
return list_targets(node.default).union(*l)
elif isinstance(node, Fragment):
return ListTargets(node.comb) | ListTargets(node.sync)
return list_targets(node.comb) | list_targets(node.sync)
else:
raise TypeError
def ListInstOuts(i):
def list_inst_outs(i):
if isinstance(i, Fragment):
return ListInstOuts(i.instances)
return list_inst_outs(i.instances)
else:
l = []
for x in i:
l += list(map(lambda x: x[1], list(x.outs.items())))
return set(l)
def IsVariable(node):
def is_variable(node):
if isinstance(node, Signal):
return node.variable
elif isinstance(node, Slice):
return IsVariable(node.value)
return is_variable(node.value)
elif isinstance(node, Cat):
arevars = list(map(IsVariable, node.l))
arevars = list(map(is_variable, node.l))
r = arevars[0]
for x in arevars:
if x != r:
@ -103,8 +103,8 @@ def IsVariable(node):
else:
raise TypeError
def InsertReset(rst, sl):
targets = ListTargets(sl)
def insert_reset(rst, sl):
targets = list_targets(sl)
resetcode = []
for t in targets:
resetcode.append(Assign(t, t.reset))

6
migen/fhdl/structure.py
View File

@ -1,6 +1,6 @@
import math
def BitsFor(n):
def bits_for(n):
if isinstance(n, Constant):
return n.bv.width
else:
@ -108,7 +108,7 @@ class Replicate(Value):
class Constant(Value):
def __init__(self, n, bv=None):
self.bv = bv or BV(BitsFor(n))
self.bv = bv or BV(bits_for(n))
self.n = n
def __repr__(self):
@ -130,7 +130,7 @@ class Signal(Value):
def __hash__(self):
return id(self)
def Declare(parent, name, bv=BV(), variable=False, reset=0):
def declare_signal(parent, name, bv=BV(), variable=False, reset=0):
# try to find a meaningful prefix
if parent.__module__ == "__main__":
prefix = parent.__class__.__name__

29
migen/fhdl/verilog.py
View File

@ -1,7 +1,8 @@
from .structure import *
from .convtools import *
from functools import partial
from migen.fhdl.structure import *
from migen.fhdl.convtools import *
def _printsig(ns, s):
if s.bv.signed:
n = "signed "
@ -9,7 +10,7 @@ def _printsig(ns, s):
n = ""
if s.bv.width > 1:
n += "[" + str(s.bv.width-1) + ":0] "
n += ns.GetName(s)
n += ns.get_name(s)
return n
def _printexpr(ns, node):
@ -19,7 +20,7 @@ def _printexpr(ns, node):
else:
return "-" + str(node.bv) + str(-self.n)
elif isinstance(node, Signal):
return ns.GetName(node)
return ns.get_name(node)
elif isinstance(node, Operator):
arity = len(node.operands)
if arity == 1:
@ -46,7 +47,7 @@ def _printexpr(ns, node):
def _printnode(ns, level, node):
if isinstance(node, Assign):
if IsVariable(node.l):
if is_variable(node.l):
assignment = " = "
else:
assignment = " <= "
@ -96,7 +97,7 @@ def _printinstances(ns, i, clk, rst):
raise TypeError
r += ")"
r += "\n) "
r += ns.GetName(x)
r += ns.get_name(x)
if x.parameters: r += " "
r += "(\n"
ports = list(x.ins.items()) + list(x.outs.items())
@ -109,7 +110,7 @@ def _printinstances(ns, i, clk, rst):
if not firstp:
r += ",\n"
firstp = False
r += "\t." + p[0] + "(" + ns.GetName(p[1]) + ")"
r += "\t." + p[0] + "(" + ns.get_name(p[1]) + ")"
if not firstp:
r += "\n"
r += ");\n\n"
@ -123,14 +124,14 @@ def Convert(f, ios=set(), name="top", clkname="sys_clk", rstname="sys_rst", ns=N
ios |= f.pads
sigs = ListSignals(f)
targets = ListTargets(f)
instouts = ListInstOuts(f)
sigs = list_signals(f)
targets = list_targets(f)
instouts = list_inst_outs(f)
r = "/* Machine-generated using Migen */\n"
r += "module " + name + "(\n"
r += "\tinput " + ns.GetName(clks) + ",\n"
r += "\tinput " + ns.GetName(rsts)
r += "\tinput " + ns.get_name(clks) + ",\n"
r += "\tinput " + ns.get_name(rsts)
for sig in ios:
if sig in targets:
r += ",\n\toutput reg " + _printsig(ns, sig)
@ -151,8 +152,8 @@ def Convert(f, ios=set(), name="top", clkname="sys_clk", rstname="sys_rst", ns=N
r += _printnode(ns, 1, f.comb)
r += "end\n\n"
if f.sync.l:
r += "always @(posedge " + ns.GetName(clks) + ") begin\n"
r += _printnode(ns, 1, InsertReset(rsts, f.sync))
r += "always @(posedge " + ns.get_name(clks) + ") begin\n"
r += _printnode(ns, 1, insert_reset(rsts, f.sync))
r += "end\n\n"
r += _printinstances(ns, f.instances, clks, rsts)