litex/migen/test/test_fifo.py

57 lines
2.0 KiB
Python
Raw Normal View History

import unittest
2015-09-19 11:20:30 -04:00
from itertools import count
from migen import *
2014-01-26 16:19:43 -05:00
from migen.genlib.fifo import SyncFIFO
2015-09-19 11:20:30 -04:00
from migen.test.support import SimCase
2015-04-13 14:45:35 -04:00
class SyncFIFOCase(SimCase, unittest.TestCase):
2015-09-19 11:20:30 -04:00
class TestBench(Module):
def __init__(self):
2015-09-30 05:06:31 -04:00
self.submodules.dut = SyncFIFO(64, 2)
self.sync += [
If(self.dut.we & self.dut.writable,
2015-09-30 05:06:31 -04:00
self.dut.din[:32].eq(self.dut.din[:32] + 1),
self.dut.din[32:].eq(self.dut.din[32:] + 2)
)
]
def test_run_sequence(self):
seq = list(range(20))
2015-09-19 11:20:30 -04:00
def gen():
for cycle in count():
# fire re and we at "random"
yield self.tb.dut.we.eq(cycle % 2 == 0)
yield self.tb.dut.re.eq(cycle % 3 == 0)
2015-09-19 11:20:30 -04:00
# the output if valid must be correct
if (yield self.tb.dut.readable) and (yield self.tb.dut.re):
try:
i = seq.pop(0)
except IndexError:
break
2015-09-30 05:06:31 -04:00
self.assertEqual((yield self.tb.dut.dout[:32]), i)
self.assertEqual((yield self.tb.dut.dout[32:]), i*2)
2015-09-19 11:20:30 -04:00
yield
self.run_with(gen())
def test_replace(self):
seq = [x for x in range(20) if x % 5]
2015-09-19 11:20:30 -04:00
def gen():
for cycle in count():
yield self.tb.dut.we.eq(cycle % 2 == 0)
yield self.tb.dut.re.eq(cycle % 7 == 0)
yield self.tb.dut.replace.eq(
2015-09-30 05:06:31 -04:00
(yield self.tb.dut.din[:32]) % 5 == 1)
2015-09-19 11:20:30 -04:00
if (yield self.tb.dut.readable) and (yield self.tb.dut.re):
try:
i = seq.pop(0)
except IndexError:
break
2015-09-30 05:06:31 -04:00
self.assertEqual((yield self.tb.dut.dout[:32]), i)
self.assertEqual((yield self.tb.dut.dout[32:]), i*2)
2015-09-19 11:20:30 -04:00
yield
self.run_with(gen())