2013-02-22 08:28:05 -05:00
|
|
|
from migen.fhdl.structure import *
|
|
|
|
from migen.bank.description import *
|
|
|
|
|
2013-09-22 12:41:44 -04:00
|
|
|
from miscope.std import *
|
2013-09-22 07:28:12 -04:00
|
|
|
from miscope.trigger import Trigger
|
2014-04-18 04:33:05 -04:00
|
|
|
from miscope.storage import Recorder, RunLengthEncoder
|
2013-09-22 07:28:12 -04:00
|
|
|
|
2013-09-21 07:04:07 -04:00
|
|
|
class MiLa(Module, AutoCSR):
|
2014-05-20 03:02:35 -04:00
|
|
|
def __init__(self, width, depth, ports, with_rle=False):
|
2013-09-22 07:28:12 -04:00
|
|
|
self.width = width
|
|
|
|
|
2013-09-22 12:41:44 -04:00
|
|
|
self.sink = rec_dat(width)
|
|
|
|
|
2013-09-22 07:28:12 -04:00
|
|
|
trigger = Trigger(width, ports)
|
|
|
|
recorder = Recorder(width, depth)
|
|
|
|
|
|
|
|
self.submodules.trigger = trigger
|
|
|
|
self.submodules.recorder = recorder
|
2013-03-21 07:23:44 -04:00
|
|
|
|
|
|
|
|
2013-09-22 12:41:44 -04:00
|
|
|
self.comb += [
|
2014-05-20 03:02:35 -04:00
|
|
|
self.sink.connect(trigger.sink),
|
|
|
|
trigger.source.connect(recorder.trig_sink)
|
2013-02-22 08:28:05 -05:00
|
|
|
]
|
2013-09-21 07:04:07 -04:00
|
|
|
|
2014-05-20 03:02:35 -04:00
|
|
|
recorder_dat_source = self.sink
|
|
|
|
if with_rle:
|
|
|
|
self.submodules.rle = RunLengthEncoder(width)
|
|
|
|
self.comb += self.sink.connect(self.rle.sink)
|
|
|
|
recorder_dat_source = self.rle.source
|
|
|
|
self.comb += recorder_dat_source.connect(recorder.dat_sink)
|