24 lines
484 B
Python
24 lines
484 B
Python
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from migen.fhdl.structure import *
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from migen.fhdl import verilog
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# convert pulse into level change
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i = Signal()
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level = Signal()
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isync = [If(i, level.eq(~level))]
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# synchronize level to oclk domain
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slevel = [Signal() for i in range(3)]
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osync = [
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slevel[0].eq(level),
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slevel[1].eq(slevel[0]),
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slevel[2].eq(slevel[1])
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]
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# regenerate pulse
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o = Signal()
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comb = [o.eq(slevel[1] ^ slevel[2])]
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f = Fragment(comb, {"i": isync, "o": osync})
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v = verilog.convert(f, ios={i, o})
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print(v)
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