litex/mibuild/altera_quartus.py

96 lines
3.5 KiB
Python
Raw Normal View History

# This file is Copyright (c) 2013 Florent Kermarrec <florent@enjoy-digital.fr>
2013-08-01 11:46:09 -04:00
# License: BSD
import os, subprocess
2013-08-26 12:08:01 -04:00
from migen.fhdl.structure import _Fragment
from mibuild.generic_platform import *
from mibuild import tools
def _format_constraint(c):
if isinstance(c, Pins):
return "set_location_assignment PIN_" + c.identifiers[0]
elif isinstance(c, IOStandard):
return "set_instance_assignment -name IO_STANDARD " + "\"" + c.name + "\""
elif isinstance(c, Misc):
return c.misc
def _format_qsf(signame, pin, others, resname):
fmt_c = [_format_constraint(c) for c in ([Pins(pin)] + others)]
fmt_r = resname[0] + ":" + str(resname[1])
if resname[2] is not None:
fmt_r += "." + resname[2]
r = ""
for c in fmt_c:
r += c + " -to " + signame + " # " + fmt_r + "\n"
return r
def _build_qsf(named_sc, named_pc):
r = ""
for sig, pins, others, resname in named_sc:
if len(pins) > 1:
for i, p in enumerate(pins):
r += _format_qsf(sig + "[" + str(i) + "]", p, others, resname)
else:
r += _format_qsf(sig, pins[0], others, resname)
if named_pc:
r += "\n" + "\n\n".join(named_pc)
r += "set_global_assignment -name top_level_entity top\n"
return r
def _build_files(device, sources, vincpaths, named_sc, named_pc, build_name):
qsf_contents = ""
for filename, language in sources:
# Enforce use of SystemVerilog (Quartus does not support global parameters in Verilog)
if language == "verilog":
language = "systemverilog"
qsf_contents += "set_global_assignment -name "+language.upper()+"_FILE " + filename.replace("\\","/") + "\n"
for path in vincpaths:
qsf_contents += "set_global_assignment -name SEARCH_PATH " + path.replace("\\","/") + "\n"
qsf_contents += _build_qsf(named_sc, named_pc)
qsf_contents += "set_global_assignment -name DEVICE " + device
tools.write_to_file(build_name + ".qsf", qsf_contents)
def _run_quartus(build_name, quartus_path):
build_script_contents = """# Autogenerated by mibuild
quartus_map --read_settings_files=on --write_settings_files=off {build_name} -c {build_name}
quartus_fit --read_settings_files=off --write_settings_files=off {build_name} -c {build_name}
quartus_asm --read_settings_files=off --write_settings_files=off {build_name} -c {build_name}
quartus_sta {build_name} -c {build_name}
""".format(build_name=build_name)
build_script_file = "build_" + build_name + ".sh"
tools.write_to_file(build_script_file, build_script_contents, force_unix=True)
r = subprocess.call(["bash", build_script_file])
if r != 0:
raise OSError("Subprocess failed")
class AlteraQuartusPlatform(GenericPlatform):
bitstream_ext = ".sof"
2013-03-15 13:46:11 -04:00
def build(self, fragment, build_dir="build", build_name="top",
quartus_path="/opt/Altera", run=True):
tools.mkdir_noerror(build_dir)
os.chdir(build_dir)
2013-08-11 17:07:07 -04:00
if not isinstance(fragment, _Fragment):
fragment = fragment.get_fragment()
self.finalize(fragment)
2013-03-15 13:46:11 -04:00
v_src, named_sc, named_pc = self.get_verilog(fragment)
v_file = build_name + ".v"
tools.write_to_file(v_file, v_src)
sources = self.sources + [(v_file, "verilog")]
_build_files(self.device, sources, self.verilog_include_paths, named_sc, named_pc, build_name)
if run:
_run_quartus(build_name, quartus_path)
os.chdir("..")
def add_period_constraint(self, clk, period):
self.add_platform_command("""set_global_assignment -name DUTY_CYCLE 50 -section_id {clk}""", clk=clk)
self.add_platform_command("""set_global_assignment -name FMAX_REQUIREMENT "{freq} MHz" -section_id {clk}\n""".format(freq=str(float(1/period)*1000), clk="{clk}"), clk=clk)