2012-02-17 05:04:44 -05:00
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from migen.fhdl.structure import *
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2013-02-24 07:07:25 -05:00
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from migen.fhdl.specials import Instance
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2013-03-10 14:32:38 -04:00
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from migen.fhdl.module import Module
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2012-02-17 05:04:44 -05:00
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from migen.bus import dfi
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2013-03-10 14:32:38 -04:00
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class S6DDRPHY(Module):
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2013-03-26 12:57:17 -04:00
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def __init__(self, pads):
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self.dfi = dfi.Interface(len(pads.a), len(pads.ba), 2*len(pads.dq), 2)
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self.clk4x_wr_strb = Signal()
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self.clk4x_rd_strb = Signal()
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###
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2012-09-10 17:47:06 -04:00
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inst_items = [
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2013-03-26 12:57:17 -04:00
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Instance.Parameter("NUM_AD", len(pads.a)),
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Instance.Parameter("NUM_BA", len(pads.ba)),
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Instance.Parameter("NUM_D", 2*len(pads.dq)),
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2013-03-18 12:44:01 -04:00
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Instance.Input("sys_clk", ClockSignal()),
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Instance.Input("clk2x_270", ClockSignal("sys2x_270")),
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Instance.Input("clk4x_wr", ClockSignal("sys4x_wr")),
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2013-03-26 12:57:17 -04:00
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Instance.Input("clk4x_rd", ClockSignal("sys4x_rd")),
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Instance.Input("clk4x_wr_strb", self.clk4x_wr_strb),
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Instance.Input("clk4x_rd_strb", self.clk4x_rd_strb),
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Instance.Output("sd_a", pads.a),
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Instance.Output("sd_ba", pads.ba),
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Instance.Output("sd_cs_n", pads.cs_n),
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Instance.Output("sd_cke", pads.cke),
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Instance.Output("sd_ras_n", pads.ras_n),
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Instance.Output("sd_cas_n", pads.cas_n),
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Instance.Output("sd_we_n", pads.we_n),
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Instance.InOut("sd_dq", pads.dq),
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Instance.Output("sd_dm", pads.dm),
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Instance.InOut("sd_dqs", pads.dqs)
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2012-09-10 17:47:06 -04:00
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]
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inst_items += [Instance.Input(name, signal)
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for name, signal in self.dfi.get_standard_names(True, False)]
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inst_items += [Instance.Output(name, signal)
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for name, signal in self.dfi.get_standard_names(False, True)]
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2013-03-10 14:32:38 -04:00
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self.specials += Instance("s6ddrphy", *inst_items)
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