Hardware
/
litex
mirror of https://github.com/enjoy-digital/litex.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Basic support for new clock domain and instance API

This commit is contained in:
Sebastien Bourdeauducq 2012-09-10 23:47:06 +02:00
parent 42d5e850fe
commit 5931c5eb59
6 changed files with 138 additions and 154 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

45
milkymist/framebuffer/__init__.py
View File

@ -172,37 +172,32 @@ class FIFO(Actor):
def get_fragment(self):
data_width = 2+3*_bpc_dac
asfifo = Instance("asfifo",
[
("data_out", BV(data_width)),
("empty", BV(1)),
("full", BV(1))
], [
("read_en", BV(1)),
("clk_read", self.vga_clk),
("data_in", BV(data_width)),
("write_en", BV(1)),
("rst", BV(1))
],
parameters=[
("data_width", data_width),
("address_width", 8)
],
clkport="clk_write")
Instance.Parameter("data_width", data_width),
Instance.Parameter("address_width", 8),
Instance.Output("data_out", BV(data_width)),
Instance.Output("empty", BV(1)),
Instance.Input("read_en", BV(1)),
Instance.Input("clk_read", self.vga_clk),
Instance.Input("data_in", BV(data_width)),
Instance.Output("full", BV(1)),
Instance.Input("write_en", BV(1)),
Instance.ClockPort("clk_write"),
Instance.Input("rst", BV(1)))
t = self.token("dac")
return Fragment(
[
asfifo.ins["read_en"].eq(1),
Cat(self.vga_hsync_n, self.vga_vsync_n, self.vga_r, self.vga_g, self.vga_b).eq(asfifo.outs["data_out"]),
asfifo.get_io("read_en").eq(1),
Cat(self.vga_hsync_n, self.vga_vsync_n, self.vga_r, self.vga_g, self.vga_b).eq(asfifo.get_io("data_out")),
self.endpoints["dac"].ack.eq(~asfifo.outs["full"]),
asfifo.ins["write_en"].eq(self.endpoints["dac"].stb),
asfifo.ins["data_in"].eq(Cat(~t.hsync, ~t.vsync, t.r, t.g, t.b)),
self.endpoints["dac"].ack.eq(~asfifo.get_io("full")),
asfifo.get_io("write_en").eq(self.endpoints["dac"].stb),
asfifo.get_io("data_in").eq(Cat(~t.hsync, ~t.vsync, t.r, t.g, t.b)),
self.busy.eq(0),
asfifo.ins["rst"].eq(0)
asfifo.get_io("rst").eq(0)
],
instances=[asfifo])

69
milkymist/lm32/__init__.py
View File

@ -8,44 +8,45 @@ class LM32:
self.interrupt = Signal(BV(32))
self.ext_break = Signal()
self._inst = Instance("lm32_top",
[("I_ADR_O", BV(32)),
("I_DAT_O", i.dat_w),
("I_SEL_O", i.sel),
("I_CYC_O", i.cyc),
("I_STB_O", i.stb),
("I_WE_O", i.we),
("I_CTI_O", i.cti),
("I_LOCK_O", BV(1)),
("I_BTE_O", i.bte),
("D_ADR_O", BV(32)),
("D_DAT_O", d.dat_w),
("D_SEL_O", d.sel),
("D_CYC_O", d.cyc),
("D_STB_O", d.stb),
("D_WE_O", d.we),
("D_CTI_O", d.cti),
("D_LOCK_O", BV(1)),
("D_BTE_O", d.bte)],
Instance.ClockPort("clk_i"),
Instance.ResetPort("rst_i"),
[("interrupt", self.interrupt),
#("ext_break", self.ext_break),
("I_DAT_I", i.dat_r),
("I_ACK_I", i.ack),
("I_ERR_I", i.err),
("I_RTY_I", BV(1)),
("D_DAT_I", d.dat_r),
("D_ACK_I", d.ack),
("D_ERR_I", d.err),
("D_RTY_I", BV(1))],
Instance.Input("interrupt", self.interrupt),
#Instance.Input("ext_break", self.ext_break),
Instance.Output("I_ADR_O", BV(32)),
Instance.Output("I_DAT_O", i.dat_w),
Instance.Output("I_SEL_O", i.sel),
Instance.Output("I_CYC_O", i.cyc),
Instance.Output("I_STB_O", i.stb),
Instance.Output("I_WE_O", i.we),
Instance.Output("I_CTI_O", i.cti),
Instance.Output("I_LOCK_O", BV(1)),
Instance.Output("I_BTE_O", i.bte),
Instance.Input("I_DAT_I", i.dat_r),
Instance.Input("I_ACK_I", i.ack),
Instance.Input("I_ERR_I", i.err),
Instance.Input("I_RTY_I", BV(1)),
clkport="clk_i",
rstport="rst_i")
Instance.Output("D_ADR_O", BV(32)),
Instance.Output("D_DAT_O", d.dat_w),
Instance.Output("D_SEL_O", d.sel),
Instance.Output("D_CYC_O", d.cyc),
Instance.Output("D_STB_O", d.stb),
Instance.Output("D_WE_O", d.we),
Instance.Output("D_CTI_O", d.cti),
Instance.Output("D_LOCK_O", BV(1)),
Instance.Output("D_BTE_O", d.bte),
Instance.Input("D_DAT_I", d.dat_r),
Instance.Input("D_ACK_I", d.ack),
Instance.Input("D_ERR_I", d.err),
Instance.Input("D_RTY_I", BV(1)))
def get_fragment(self):
comb = [
self._inst.ins["I_RTY_I"].eq(0),
self._inst.ins["D_RTY_I"].eq(0),
self.ibus.adr.eq(self._inst.outs["I_ADR_O"][2:]),
self.dbus.adr.eq(self._inst.outs["D_ADR_O"][2:])
self._inst.get_io("I_RTY_I").eq(0),
self._inst.get_io("D_RTY_I").eq(0),
self.ibus.adr.eq(self._inst.get_io("I_ADR_O")[2:]),
self.dbus.adr.eq(self._inst.get_io("D_ADR_O")[2:])
]
return Fragment(comb=comb, instances=[self._inst])

38
milkymist/m1crg/__init__.py
View File

@ -7,10 +7,23 @@ class M1CRG:
self.clkin = Signal()
self.trigger_reset = Signal()
generated = []
self.cd_sys = ClockDomain("sys")
ratio = Fraction(outfreq1x)/Fraction(infreq)
in_period = float(Fraction(1000000000)/Fraction(infreq))
inst_items = [
Instance.Parameter("in_period", in_period),
Instance.Parameter("f_mult", ratio.numerator),
Instance.Parameter("f_div", ratio.denominator),
Instance.Input("clkin", self.clkin),
Instance.Input("trigger_reset", self.trigger_reset),
Instance.Output("sys_clk", self.cd_sys.clk),
Instance.Output("sys_rst", self.cd_sys.rst)
]
for name in [
"sys_clk",
"sys_rst",
"ac97_rst_n",
"videoin_rst_n",
"flash_rst_n",
@ -25,23 +38,10 @@ class M1CRG:
]:
s = Signal(name=name)
setattr(self, name, s)
generated.append((name, s))
inst_items.append(Instance.Output(name, s))
ratio = Fraction(outfreq1x)/Fraction(infreq)
in_period = float(Fraction(1000000000)/Fraction(infreq))
self._inst = Instance("m1crg",
generated,
[
("clkin", self.clkin),
("trigger_reset", self.trigger_reset)
],
parameters=[
("in_period", in_period),
("f_mult", ratio.numerator),
("f_div", ratio.denominator)
]
)
self._inst = Instance("m1crg", *inst_items)
def get_fragment(self):
return Fragment(instances=[self._inst])

72
milkymist/minimac3/__init__.py
View File

@ -61,45 +61,39 @@ class MiniMAC:
]
inst = [
Instance("minimac3",
[
("rx_done_0", self._rx_event_0.trigger),
("rx_count_0", self._rx_count_0.field.w),
("rx_done_1", self._rx_event_1.trigger),
("rx_count_1", self._rx_count_1.field.w),
("tx_done", self._tx_event.trigger),
("wb_dat_o", self.membus.dat_r),
("wb_ack_o", self.membus.ack),
("phy_tx_data", self.phy_tx_data),
("phy_tx_en", self.phy_tx_en),
("phy_tx_er", self.phy_tx_er),
], [
("rx_ready_0", rx_ready_0),
("rx_ready_1", rx_ready_1),
("tx_start", self._tx_start.re),
("tx_count", self._tx_count.field.r),
("wb_adr_i", self.membus.adr),
("wb_dat_i", self.membus.dat_w),
("wb_sel_i", self.membus.sel),
("wb_stb_i", self.membus.stb),
("wb_cyc_i", self.membus.cyc),
("wb_we_i", self.membus.we),
("phy_tx_clk", self.phy_tx_clk),
("phy_rx_clk", self.phy_rx_clk),
("phy_rx_data", self.phy_rx_data),
("phy_dv", self.phy_dv),
("phy_rx_er", self.phy_rx_er),
("phy_col", self.phy_col),
("phy_crs", self.phy_crs)
],
clkport="sys_clk",
rstport="sys_rst"
)
Instance.ClockPort("sys_clk"),
Instance.ResetPort("sys_rst"),
Instance.Output("rx_done_0", self._rx_event_0.trigger),
Instance.Output("rx_count_0", self._rx_count_0.field.w),
Instance.Output("rx_done_1", self._rx_event_1.trigger),
Instance.Output("rx_count_1", self._rx_count_1.field.w),
Instance.Input("rx_ready_0", rx_ready_0),
Instance.Input("rx_ready_1", rx_ready_1),
Instance.Input("tx_start", self._tx_start.re),
Instance.Input("tx_count", self._tx_count.field.r),
Instance.Output("tx_done", self._tx_event.trigger),
Instance.Input("wb_adr_i", self.membus.adr),
Instance.Input("wb_dat_i", self.membus.dat_w),
Instance.Input("wb_sel_i", self.membus.sel),
Instance.Input("wb_stb_i", self.membus.stb),
Instance.Input("wb_cyc_i", self.membus.cyc),
Instance.Input("wb_we_i", self.membus.we),
Instance.Output("wb_dat_o", self.membus.dat_r),
Instance.Output("wb_ack_o", self.membus.ack),
Instance.Output("phy_tx_data", self.phy_tx_data),
Instance.Output("phy_tx_en", self.phy_tx_en),
Instance.Output("phy_tx_er", self.phy_tx_er),
Instance.Input("phy_tx_clk", self.phy_tx_clk),
Instance.Input("phy_rx_clk", self.phy_rx_clk),
Instance.Input("phy_rx_data", self.phy_rx_data),
Instance.Input("phy_dv", self.phy_dv),
Instance.Input("phy_rx_er", self.phy_rx_er),
Instance.Input("phy_col", self.phy_col),
Instance.Input("phy_crs", self.phy_crs))
]
return Fragment(comb, sync, instances=inst) \
+ self.events.get_fragment() \

65
milkymist/s6ddrphy/__init__.py
View File

@ -3,49 +3,44 @@ from migen.bus import dfi
class S6DDRPHY:
def __init__(self, a, ba, d):
ins = []
outs = []
inouts = []
for name, width, l in [
("clk2x_270", 1, ins),
("clk4x_wr", 1, ins),
("clk4x_wr_strb", 1, ins),
("clk4x_rd", 1, ins),
("clk4x_rd_strb", 1, ins),
inst_items = [
Instance.Parameter("NUM_AD", a),
Instance.Parameter("NUM_BA", ba),
Instance.Parameter("NUM_D", d),
Instance.ClockPort("sys_clk")
]
for name, width, cl in [
("clk2x_270", 1, Instance.Input),
("clk4x_wr", 1, Instance.Input),
("clk4x_wr_strb", 1, Instance.Input),
("clk4x_rd", 1, Instance.Input),
("clk4x_rd_strb", 1, Instance.Input),
("sd_clk_out_p", 1, outs),
("sd_clk_out_n", 1, outs),
("sd_a", a, outs),
("sd_ba", ba, outs),
("sd_cs_n", 1, outs),
("sd_cke", 1, outs),
("sd_ras_n", 1, outs),
("sd_cas_n", 1, outs),
("sd_we_n", 1, outs),
("sd_dq", d//2, inouts),
("sd_dm", d//16, outs),
("sd_dqs", d//16, inouts)
("sd_clk_out_p", 1, Instance.Output),
("sd_clk_out_n", 1, Instance.Output),
("sd_a", a, Instance.Output),
("sd_ba", ba, Instance.Output),
("sd_cs_n", 1, Instance.Output),
("sd_cke", 1, Instance.Output),
("sd_ras_n", 1, Instance.Output),
("sd_cas_n", 1, Instance.Output),
("sd_we_n", 1, Instance.Output),
("sd_dq", d//2, Instance.InOut),
("sd_dm", d//16, Instance.Output),
("sd_dqs", d//16, Instance.InOut)
]:
s = Signal(BV(width), name=name)
setattr(self, name, s)
l.append((name, s))
inst_items.append(cl(name, s))
self.dfi = dfi.Interface(a, ba, d, 2)
ins += self.dfi.get_standard_names(True, False)
outs += self.dfi.get_standard_names(False, True)
inst_items += [Instance.Input(name, signal)
for name, signal in self.dfi.get_standard_names(True, False)]
inst_items += [Instance.Output(name, signal)
for name, signal in self.dfi.get_standard_names(False, True)]
self._inst = Instance("s6ddrphy",
outs,
ins,
inouts,
[
("NUM_AD", a),
("NUM_BA", ba),
("NUM_D", d)
],
clkport="sys_clk")
self._inst = Instance("s6ddrphy", *inst_items)
def get_fragment(self):
return Fragment(instances=[self._inst])

3
top.py
View File

@ -160,8 +160,7 @@ def get():
src_verilog, vns = verilog.convert(frag,
cst.get_ios(),
name="soc",
clk_signal=crg0.sys_clk,
rst_signal=crg0.sys_rst,
clock_domains={"sys": crg0.cd_sys},
return_ns=True)
src_ucf = cst.get_ucf(vns)
return (src_verilog, src_ucf)