2015-09-12 07:34:07 -04:00
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from migen import *
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2012-09-09 13:34:46 -04:00
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from migen.fhdl import verilog
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2015-09-10 16:56:56 -04:00
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from functools import reduce
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from operator import or_
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2012-09-09 13:34:46 -04:00
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2015-04-13 14:45:35 -04:00
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2012-09-09 13:34:46 -04:00
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def gen_list(n):
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2015-04-13 14:07:07 -04:00
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s = [Signal() for i in range(n)]
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return s
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2012-09-09 13:34:46 -04:00
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2015-04-13 14:45:35 -04:00
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2012-09-09 13:34:46 -04:00
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def gen_2list(n):
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2015-04-13 14:07:07 -04:00
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s = [Signal(2) for i in range(n)]
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return s
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2012-09-09 13:34:46 -04:00
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2015-04-13 14:45:35 -04:00
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2012-09-09 13:34:46 -04:00
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class Foo:
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2015-04-13 14:07:07 -04:00
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def __init__(self):
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la = gen_list(3)
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lb = gen_2list(2)
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self.sigs = la + lb
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2012-09-09 13:34:46 -04:00
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2015-04-13 14:45:35 -04:00
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2012-09-09 13:34:46 -04:00
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class Bar:
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2015-04-13 14:07:07 -04:00
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def __init__(self):
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self.sigs = gen_list(2)
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2012-09-09 13:34:46 -04:00
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2015-04-13 14:45:35 -04:00
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2013-03-12 11:45:28 -04:00
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class Example(Module):
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2015-04-13 14:07:07 -04:00
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def __init__(self):
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a = [Bar() for x in range(3)]
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b = [Foo() for x in range(3)]
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c = b
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b = [Bar() for x in range(2)]
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2012-09-09 13:34:46 -04:00
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2015-04-13 14:07:07 -04:00
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output = Signal()
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allsigs = []
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for lst in [a, b, c]:
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for obj in lst:
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allsigs.extend(obj.sigs)
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2015-09-10 16:56:56 -04:00
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self.comb += output.eq(reduce(or_, allsigs))
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2012-09-09 13:34:46 -04:00
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2013-03-12 11:45:28 -04:00
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print(verilog.convert(Example()))
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