2015-01-28 13:07:59 -05:00
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import binascii
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from liteeth.common import *
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from liteeth.mac.common import *
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from liteeth.test.common import *
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2015-01-28 14:44:41 -05:00
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def print_mac(s):
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print_with_prefix(s, "[MAC]")
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preamble = [0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xD5]
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2015-01-28 13:07:59 -05:00
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def crc32(l):
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crc = []
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crc_bytes = binascii.crc32(bytes(l)).to_bytes(4, byteorder="little")
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for byte in crc_bytes:
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crc.append(int(byte))
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return crc
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# MAC model
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class MACPacket(list):
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def __init__(self, init=[]):
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self.ongoing = False
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self.done = False
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for byte in init:
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self.append(byte)
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class MACRXPacket(MACPacket):
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def check_remove_preamble(self):
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2015-01-28 14:44:41 -05:00
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if comp(self[0:8], preamble):
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2015-01-28 13:07:59 -05:00
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for i in range(8):
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self.pop(0)
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return False
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else:
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return True
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def check_remove_crc(self):
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if comp(self[-4:], crc32(self[:-4])):
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for i in range(4):
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self.pop()
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return False
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else:
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return True
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class MACTXPacket(MACPacket):
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def insert_crc(self):
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2015-01-28 14:44:41 -05:00
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for d in crc32(self):
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self.append(d)
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2015-01-28 13:07:59 -05:00
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def insert_preamble(self):
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2015-01-28 14:44:41 -05:00
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for d in reversed(preamble):
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self.insert(0, d)
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2015-01-28 13:07:59 -05:00
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class MAC(Module):
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2015-01-28 14:44:41 -05:00
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def __init__(self, phy, debug=False, loopback=False):
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2015-01-28 13:07:59 -05:00
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self.phy = phy
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self.debug = debug
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2015-01-28 14:44:41 -05:00
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self.loopback = loopback
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2015-01-28 13:07:59 -05:00
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self.tx_packets = []
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self.tx_packet = MACTXPacket()
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self.rx_packet = MACRXPacket()
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self.ip_callback = None
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def set_ip_callback(self, callback):
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self.ip_callback = callback
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def send(self, datas):
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tx_packet = MACTXPacket(datas)
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2015-01-28 14:44:41 -05:00
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if self.debug:
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r = ">>>>>>>>\n"
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r += "length " + str(len(tx_packet)) + "\n"
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for d in tx_packet:
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r += "%02x" %d
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print_mac(r)
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2015-01-28 13:07:59 -05:00
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tx_packet.insert_crc()
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tx_packet.insert_preamble()
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self.tx_packets.append(tx_packet)
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def callback(self, datas):
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rx_packet = MACRXPacket(datas)
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preamble_error = rx_packet.check_remove_preamble()
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crc_error = rx_packet.check_remove_crc()
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2015-01-28 14:44:41 -05:00
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if self.debug:
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r = "<<<<<<<<\n"
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r += "preamble_error " + str(preamble_error) + "\n"
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r += "crc_error " + str(crc_error) + "\n"
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r += "length " + str(len(rx_packet)) + "\n"
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for d in rx_packet:
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r += "%02x" %d
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print_mac(r)
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2015-01-28 13:07:59 -05:00
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if (not preamble_error) and (not crc_error):
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2015-01-28 14:44:41 -05:00
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if self.loopback:
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self.send(rx_packet)
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elif self.ip_callback is not None:
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2015-01-28 13:07:59 -05:00
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self.ip_callback(rx_packet)
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def gen_simulation(self, selfp):
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self.tx_packet.done = True
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while True:
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yield from self.phy.receive()
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self.callback(self.phy.packet)
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# XXX add full duplex
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if len(self.tx_packets) != 0:
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tx_packet = self.tx_packets.pop(0)
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yield from self.phy.send(tx_packet)
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