test: add mac simulation skeleton
This commit is contained in:
Florent Kermarrec
parent
8a42d74904
commit
33edf11ec9
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@ -5,6 +5,7 @@ from migen.fhdl.std import *
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from migen.genlib.resetsync import AsyncResetSynchronizer
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from migen.genlib.record import *
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from migen.genlib.fsm import FSM, NextState
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from migen.genlib.misc import chooser
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from migen.flow.actor import EndpointDescription
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from migen.flow.actor import Sink, Source
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from migen.actorlib.structuring import Converter, Pipeline
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@ -16,8 +16,8 @@ class LiteEthMACCore(Module, AutoCSR):
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self.submodules += RenameClockDomains(preamble_checker, "eth_rx")
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# CRC insert/check
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crc32_inserter = crc.LiteEthMACCRC32Inserter(eth_description(phy.dw))
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crc32_checker = crc.LiteEthMACCRC32Checker(eth_description(phy.dw))
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crc32_inserter = crc.LiteEthMACCRC32Inserter(eth_phy_description(phy.dw))
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crc32_checker = crc.LiteEthMACCRC32Checker(eth_phy_description(phy.dw))
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self.submodules += RenameClockDomains(crc32_inserter, "eth_tx")
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self.submodules += RenameClockDomains(crc32_checker, "eth_rx")
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@ -101,7 +101,7 @@ class LiteEthMACCRC32(Module):
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###
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self.submodules.engine = LiteEthCRCEngine(data_width, self.width, self.polynom)
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self.submodules.engine = LiteEthMACCRCEngine(data_width, self.width, self.polynom)
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reg = Signal(self.width, reset=self.init)
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self.sync += reg.eq(self.engine.next)
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self.comb += [
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@ -255,14 +255,14 @@ class LiteEthMACCRCChecker(Module):
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NextState("IDLE"),
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)
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fsm.act("IDLE",
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crc.d.eq(sink.data),
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crc.data.eq(sink.data),
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If(sink.stb & sink.sop & sink.ack,
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crc.ce.eq(1),
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NextState("COPY")
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)
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)
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fsm.act("COPY",
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crc.d.eq(sink.data),
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crc.data.eq(sink.data),
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If(sink.stb & sink.ack,
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crc.ce.eq(1),
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If(sink.eop,
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@ -1,7 +1,7 @@
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LEDIR = ../../
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PYTHON = python3
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CMD = PYTHONPATH=$(MSCDIR) $(PYTHON)
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CMD = PYTHONPATH=$(LEDIR) $(PYTHON)
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mac_core_tb:
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$(CMD) mac_core_tb.py
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@ -4,7 +4,7 @@ from migen.fhdl.std import *
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from migen.flow.actor import Sink, Source
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from migen.genlib.record import *
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from misoclib.ethmac.common import *
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from liteeth.common import *
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def print_with_prefix(s, prefix=""):
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if not isinstance(s, str):
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@ -19,6 +19,13 @@ def seed_to_data(seed, random=True):
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else:
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return seed
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def comp(p1, p2):
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r = True
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for x, y in zip(p1, p2):
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if x != y:
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r = False
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return r
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def check(p1, p2):
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p1 = copy.deepcopy(p1)
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p2 = copy.deepcopy(p2)
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@ -51,16 +58,19 @@ class Packet(list):
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self.append(data)
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class PacketStreamer(Module):
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def __init__(self, description):
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def __init__(self, description, last_be=None):
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self.source = Source(description)
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self.last_be = last_be
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###
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self.packets = []
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self.packet = Packet()
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self.packet.done = 1
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self.packet.done = True
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def send(self, packet):
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packet = copy.deepcopy(packet)
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self.packets.append(packet)
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while not packet.done:
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yield
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def do_simulation(self, selfp):
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if len(self.packets) and self.packet.done:
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@ -68,16 +78,22 @@ class PacketStreamer(Module):
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if not self.packet.ongoing and not self.packet.done:
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selfp.source.stb = 1
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selfp.source.sop = 1
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selfp.source.d = self.packet.pop(0)
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selfp.source.data = self.packet.pop(0)
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self.packet.ongoing = True
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elif selfp.source.stb == 1 and selfp.source.ack == 1:
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selfp.source.sop = 0
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selfp.source.eop = (len(self.packet) == 1)
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if len(self.packet) == 1:
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selfp.source.eop = 1
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if self.last_be is not None:
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selfp.source.last_be = self.last_be
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else:
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selfp.source.eop = 0
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selfp.source.last_be = 0
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if len(self.packet) > 0:
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selfp.source.stb = 1
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selfp.source.d = self.packet.pop(0)
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selfp.source.data = self.packet.pop(0)
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else:
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self.packet.done = 1
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self.packet.done = True
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selfp.source.stb = 0
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class PacketLogger(Module):
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@ -87,17 +103,17 @@ class PacketLogger(Module):
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self.packet = Packet()
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def receive(self):
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self.packet.done = 0
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while self.packet.done == 0:
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self.packet.done = False
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while not self.packet.done:
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yield
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def do_simulation(self, selfp):
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selfp.sink.ack = 1
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if selfp.sink.stb == 1 and selfp.sink.sop == 1:
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self.packet = Packet()
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self.packet.append(selfp.sink.d)
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self.packet.append(selfp.sink.data)
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elif selfp.sink.stb:
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self.packet.append(selfp.sink.d)
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self.packet.append(selfp.sink.data)
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if selfp.sink.stb == 1 and selfp.sink.eop == 1:
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self.packet.done = True
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@ -3,69 +3,23 @@ from migen.bus import wishbone
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from migen.bus.transactions import *
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from migen.sim.generic import run_simulation
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from misoclib.ethmac import EthMAC
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from misoclib.ethmac.phy import loopback
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from liteeth.common import *
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from liteeth.mac import LiteEthMAC
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from misoclib.ethmac.test.common import *
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class WishboneMaster:
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def __init__(self, obj):
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self.obj = obj
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self.dat = 0
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def write(self, adr, dat):
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self.obj.cyc = 1
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self.obj.stb = 1
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self.obj.adr = adr
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self.obj.we = 1
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self.obj.sel = 0xF
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self.obj.dat_w = dat
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while self.obj.ack == 0:
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yield
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self.obj.cyc = 0
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self.obj.stb = 0
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yield
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def read(self, adr):
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self.obj.cyc = 1
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self.obj.stb = 1
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self.obj.adr = adr
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self.obj.we = 0
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self.obj.sel = 0xF
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self.obj.dat_w = 0
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while self.obj.ack == 0:
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yield
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self.dat = self.obj.dat_r
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self.obj.cyc = 0
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self.obj.stb = 0
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yield
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class SRAMReaderDriver:
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def __init__(self, obj):
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self.obj = obj
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def start(self, slot, length):
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self.obj._slot.storage = slot
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self.obj._length.storage = length
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self.obj._start.re = 1
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yield
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self.obj._start.re = 0
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yield
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def wait_done(self):
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while self.obj.ev.done.pending == 0:
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yield
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def clear_done(self):
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self.obj.ev.done.clear = 1
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yield
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self.obj.ev.done.clear = 0
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yield
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from liteeth.test.common import *
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from liteeth.test.model import phy, mac
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class TB(Module):
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def __init__(self):
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self.submodules.ethphy = loopback.LoopbackPHY()
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self.submodules.ethmac = EthMAC(phy=self.ethphy, with_hw_preamble_crc=True)
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self.submodules.hostphy = phy.PHY(8, debug=True)
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self.submodules.hostmac = mac.MAC(self.hostphy, debug=True, random_level=0)
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self.submodules.ethmac = LiteEthMAC(phy=self.hostphy, dw=32, interface="core", with_hw_preamble_crc=True)
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self.submodules.streamer = PacketStreamer(eth_mac_description(32), last_be=1)
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self.submodules.streamer_randomizer = AckRandomizer(eth_mac_description(32), level=0)
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self.submodules.logger_randomizer = AckRandomizer(eth_mac_description(32), level=0)
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self.submodules.logger = PacketLogger(eth_mac_description(32))
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# use sys_clk for each clock_domain
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self.clock_domains.cd_eth_rx = ClockDomain()
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@ -77,6 +31,13 @@ class TB(Module):
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self.cd_eth_tx.rst.eq(ResetSignal()),
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]
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self.comb += [
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Record.connect(self.streamer.source, self.streamer_randomizer.sink),
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Record.connect(self.streamer_randomizer.source, self.ethmac.sink),
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Record.connect(self.ethmac.source, self.logger_randomizer.sink),
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Record.connect(self.logger_randomizer.source, self.logger.sink)
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]
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def gen_simulation(self, selfp):
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selfp.cd_eth_rx.rst = 1
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selfp.cd_eth_tx.rst = 1
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@ -84,40 +45,10 @@ class TB(Module):
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selfp.cd_eth_rx.rst = 0
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selfp.cd_eth_tx.rst = 0
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wishbone_master = WishboneMaster(selfp.ethmac.bus)
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sram_reader_driver = SRAMReaderDriver(selfp.ethmac.sram_reader)
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sram_writer_slots_offset = [0x000, 0x200]
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sram_reader_slots_offset = [0x400, 0x600]
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length = 1500+2
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tx_payload = [seed_to_data(i, True) % 0xFF for i in range(length)] + [0, 0, 0, 0]
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errors = 0
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for slot in range(2):
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print("slot {}:".format(slot))
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# fill tx memory
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for i in range(length//4+1):
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dat = int.from_bytes(tx_payload[4*i:4*(i+1)], "big")
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yield from wishbone_master.write(sram_reader_slots_offset[slot]+i, dat)
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# send tx payload & wait
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yield from sram_reader_driver.start(slot, length)
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yield from sram_reader_driver.wait_done()
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yield from sram_reader_driver.clear_done()
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# get rx payload (loopback on PHY Model)
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rx_payload = []
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for i in range(length//4+1):
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yield from wishbone_master.read(sram_writer_slots_offset[slot]+i)
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dat = wishbone_master.dat
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rx_payload += list(dat.to_bytes(4, byteorder='big'))
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# check results
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s, l, e = check(tx_payload[:length], rx_payload[:min(length, len(rx_payload))])
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print("shift "+ str(s) + " / length " + str(l) + " / errors " + str(e))
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for i in range(8):
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streamer_packet = Packet([i for i in range(64)])
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print(streamer_packet)
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yield from self.streamer.send(streamer_packet)
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if __name__ == "__main__":
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run_simulation(TB(), vcd_name="my.vcd")
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run_simulation(TB(), ncycles=1000, vcd_name="my.vcd", keep_files=True)
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@ -0,0 +1,82 @@
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import binascii
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from liteeth.common import *
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from liteeth.mac.common import *
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from liteeth.test.common import *
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def crc32(l):
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crc = []
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crc_bytes = binascii.crc32(bytes(l)).to_bytes(4, byteorder="little")
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for byte in crc_bytes:
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crc.append(int(byte))
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return crc
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# MAC model
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class MACPacket(list):
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def __init__(self, init=[]):
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self.ongoing = False
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self.done = False
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for byte in init:
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self.append(byte)
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class MACRXPacket(MACPacket):
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def check_remove_preamble(self):
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if comp(self[0:8], [0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xD5]):
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for i in range(8):
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self.pop(0)
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return False
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else:
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return True
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def check_remove_crc(self):
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if comp(self[-4:], crc32(self[:-4])):
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for i in range(4):
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self.pop()
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return False
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else:
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return True
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class MACTXPacket(MACPacket):
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def insert_crc(self):
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return self
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def insert_preamble(self):
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return self
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class MAC(Module):
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def __init__(self, phy, debug=False, random_level=0):
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self.phy = phy
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self.debug = debug
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self.random_level = random_level
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self.tx_packets = []
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self.tx_packet = MACTXPacket()
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self.rx_packet = MACRXPacket()
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self.ip_callback = None
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def set_ip_callback(self, callback):
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self.ip_callback = callback
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def send(self, datas):
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tx_packet = MACTXPacket(datas)
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tx_packet.insert_crc()
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tx_packet.insert_preamble()
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self.tx_packets.append(tx_packet)
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def callback(self, datas):
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rx_packet = MACRXPacket(datas)
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preamble_error = rx_packet.check_remove_preamble()
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crc_error = rx_packet.check_remove_crc()
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if (not preamble_error) and (not crc_error):
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if self.ip_callback is not None:
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self.ip_callback(rx_packet)
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def gen_simulation(self, selfp):
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self.tx_packet.done = True
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while True:
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yield from self.phy.receive()
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self.callback(self.phy.packet)
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# XXX add full duplex
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if len(self.tx_packets) != 0:
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tx_packet = self.tx_packets.pop(0)
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yield from self.phy.send(tx_packet)
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@ -16,13 +16,18 @@ class PHY(Module):
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self.dw = dw
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self.debug = debug
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self.phy_source = PHYSource(dw)
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self.phy_sink = PHYSink(dw)
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self.submodules.phy_source = PHYSource(dw)
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self.submodules.phy_sink = PHYSink(dw)
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self.source = self.phy_source.source
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self.sink = self.phy_sink.sink
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def send(self, datas, blocking=True):
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self.mac_callback = None
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def set_mac_callback(self, callback):
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self.mac_callback = callback
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def send(self, datas):
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packet = Packet(datas)
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yield from self.phy_source.send(packet, blocking)
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