2015-09-12 07:34:07 -04:00
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from migen import *
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2013-11-29 03:47:32 -05:00
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from migen.fhdl import verilog
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2015-04-13 14:45:35 -04:00
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2013-11-30 08:51:24 -05:00
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class SimCase:
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2015-04-13 14:07:07 -04:00
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def setUp(self, *args, **kwargs):
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self.tb = self.TestBench(*args, **kwargs)
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2013-11-29 03:47:32 -05:00
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2015-04-13 14:07:07 -04:00
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def test_to_verilog(self):
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verilog.convert(self.tb)
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2013-11-29 03:47:32 -05:00
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2015-09-12 04:28:21 -04:00
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def run_with(self, generator):
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2015-09-21 09:20:31 -04:00
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run_simulation(self.tb, generator)
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