litex/migen/bank/csrgen.py

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from operator import itemgetter
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from migen.fhdl.structure import *
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from migen.fhdl.module import Module
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from migen.bus import csr
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from migen.bank.description import *
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class Bank(Module):
def __init__(self, description, address=0, bus=None):
if bus is None:
bus = csr.Interface()
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self.bus = bus
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###
if not description:
return
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# Turn description into simple CSRs and claim ownership of compound CSR modules
simple_csrs = []
for c in description:
if isinstance(c, CSR):
simple_csrs.append(c)
else:
c.finalize(csr.data_width)
simple_csrs += c.get_simple_csrs()
self.submodules += c
nbits = bits_for(len(simple_csrs)-1)
# Decode selection
sel = Signal()
self.comb += sel.eq(self.bus.adr[9:] == address)
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# Bus writes
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for i, c in enumerate(simple_csrs):
self.comb += [
c.r.eq(self.bus.dat_w[:c.size]),
c.re.eq(sel & \
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self.bus.we & \
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(self.bus.adr[:nbits] == i))
]
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# Bus reads
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brcases = dict((i, self.bus.dat_r.eq(c.w)) for i, c in enumerate(simple_csrs))
self.sync += [
self.bus.dat_r.eq(0),
If(sel, Case(self.bus.adr[:nbits], brcases))
]
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# address_map(name, memory) returns the CSR offset at which to map
# the CSR object (register bank or memory).
# If memory=None, the object is the register bank of object source.name.
# Otherwise, it is a memory object belonging to source.name.
# address_map is called exactly once for each object at each call to
# scan(), so it can have side effects.
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class BankArray(Module):
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def __init__(self, source, address_map):
self.source = source
self.address_map = address_map
self.scan()
def scan(self):
self.banks = []
self.srams = []
for name, obj in sorted(self.source.__dict__.items(), key=itemgetter(0)):
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if hasattr(obj, "get_csrs"):
csrs = obj.get_csrs()
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else:
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csrs = []
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if hasattr(obj, "get_memories"):
memories = obj.get_memories()
for memory in memories:
mapaddr = self.address_map(name, memory)
mmap = csr.SRAM(memory, mapaddr)
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self.submodules += mmap
csrs += mmap.get_csrs()
self.srams.append((name, memory, mapaddr, mmap))
if csrs:
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mapaddr = self.address_map(name, None)
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rmap = Bank(csrs, mapaddr)
self.submodules += rmap
self.banks.append((name, csrs, mapaddr, rmap))
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def get_rmaps(self):
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return [rmap for name, csrs, mapaddr, rmap in self.banks]
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def get_mmaps(self):
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return [mmap for name, memory, mapaddr, mmap in self.srams]
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def get_buses(self):
return [i.bus for i in self.get_rmaps() + self.get_mmaps()]