2013-09-03 18:01:33 -04:00
|
|
|
from migen.fhdl.std import *
|
|
|
|
from migen.flow.actor import *
|
|
|
|
from migen.genlib import fifo
|
|
|
|
|
2013-09-04 11:22:50 -04:00
|
|
|
class _FIFOActor(Module):
|
|
|
|
def __init__(self, fifo_class, layout, depth):
|
2013-09-03 18:01:33 -04:00
|
|
|
self.sink = Sink(layout)
|
|
|
|
self.source = Source(layout)
|
|
|
|
self.busy = Signal()
|
|
|
|
|
2013-09-04 11:22:50 -04:00
|
|
|
###
|
2013-09-03 18:01:33 -04:00
|
|
|
|
2013-09-04 11:22:50 -04:00
|
|
|
self.submodules.fifo = fifo_class(layout, depth)
|
2013-09-03 18:01:33 -04:00
|
|
|
|
2013-09-04 11:22:50 -04:00
|
|
|
self.comb += [
|
|
|
|
self.sink.ack.eq(self.fifo.writable),
|
|
|
|
self.fifo.we.eq(self.sink.stb & self.sink.ack),
|
|
|
|
self.fifo.din.eq(self.sink.payload),
|
2013-09-03 18:01:33 -04:00
|
|
|
|
2013-09-04 11:22:50 -04:00
|
|
|
self.source.stb.eq(self.fifo.readable),
|
|
|
|
self.source.payload.eq(self.fifo.dout),
|
|
|
|
self.fifo.re.eq(self.source.ack)
|
|
|
|
]
|
2013-09-03 18:01:33 -04:00
|
|
|
|
|
|
|
|
2013-09-04 11:22:50 -04:00
|
|
|
class SyncFIFO(_FIFOActor):
|
|
|
|
def __init__(self, layout, depth):
|
|
|
|
_FIFOActor.__init__(self, fifo.SyncFIFO, layout, depth)
|
2013-09-03 18:01:33 -04:00
|
|
|
|
2013-09-04 11:22:50 -04:00
|
|
|
class AsyncFIFO(_FIFOActor):
|
|
|
|
def __init__(self, layout, depth):
|
|
|
|
_FIFOActor.__init__(self, fifo.AsyncFIFO, layout, depth)
|