124 lines
4.0 KiB
Plaintext
124 lines
4.0 KiB
Plaintext
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/ / (_) /____ / _ \/ ___/ _/__
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/ /__/ / __/ -_) ___/ /___/ // -_)
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/____/_/\__/\__/_/ \___/___/\__/
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Copyright 2015 / EnjoyDigital / M-Labs Ltd
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A small footprint and configurable PCIe core
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with MMAP interface and scatter-gather DMA
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developed by EnjoyDigital
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[> Doc
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---------
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XXX
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[> Intro
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---------
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LitePCIe provides a small footprint and configurable PCIe gen1/2 core.
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LitePCIe is part of MiSoC libraries whose aims are to lower entry level of
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complex FPGA cores by providing simple, elegant and efficient implementations
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ofcomponents used in today's SoC such as Ethernet, SATA, PCIe, SDRAM Controller...
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The core uses simple and specific streaming buses and will provides in the future
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adapters to use standardized AXI or Avalon-ST streaming buses.
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Since Python is used to describe the HDL, the core is highly and easily
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configurable.
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LitePCIe uses technologies developed in partnership with M-Labs Ltd:
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- Migen enables generating HDL with Python in an efficient way.
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- MiSoC provides the basic blocks to build a powerful and small footprint SoC.
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LitePCIe can be used as MiSoC library or can be integrated with your standard
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design flow by generating the verilog rtl that you will use as a standard core.
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[> Features
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-----------
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- 7-Series Artix7/Kintex7 PHY (up to PCIe Gen2 X2)
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- Scatter-gather DMA
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- Wishbone bridge
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- Linux driver with DMA loopback demo and Sysfs
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[> Possibles improvements
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-------------------------
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- add standardized interfaces (AXI, Avalon-ST)
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- add support for PCIe Gen2 X4 and X8 on 7-Series
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- clean up 7-Series wrappers
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- add Altera/Lattice support
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- ... See below Support and consulting :)
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If you want to support these features, please contact us at florent [AT]
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enjoy-digital.fr. You can also contact our partner on the public mailing list
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devel [AT] lists.m-labs.hk.
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[> Getting started
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------------------
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1. Install Python3 and your vendor's software
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2. Obtain Migen and install it:
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git clone https://github.com/m-labs/migen
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cd migen
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python3 setup.py install
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cd ..
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3. Obtain MiSoC:
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git clone https://github.com/m-labs/misoc --recursive
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4. Build and load PCIe DMA loopback design (only for KC705 for now):
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go to misoclib/com/litepcie/example_designs/
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run ./make.py all load-bitstream
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5. Build and load Linux Driver:
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go to misoclib/com/litepcie/software/linux/kernel
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make all
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./init.sh
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5. Build and load Linux utilities:
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go to misoclib/com/litepcie/software/linux/user
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make all
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./litepcie_util dma_loopback_test
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[> Simulations:
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Simulations are available in misoclib/com/litepcie/test:
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- wishbone_tb
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- dma_tb
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To run a simulation, move to misoclib/com/litepcie/test/ and run:
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make simulation_name
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[> Tests :
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A DMA loopback example with Wishbone over Sysfs is provided.
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Please go to Getting Started section to see how to run the tests.
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[> License
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-----------
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LitePCIe is released under the very permissive two-clause BSD license. Under
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the terms of this license, you are authorized to use LiteEth for closed-source
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proprietary designs.
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Even though we do not require you to do so, those things are awesome, so please
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do them if possible:
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- tell us that you are using LitePCIe
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- cite LitePCIe in publications related to research it has helped
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- send us feedback and suggestions for improvements
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- send us bug reports when something goes wrong
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- send us the modifications and improvements you have done to LitePCIe.
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[> Support and consulting
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--------------------------
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We love open-source hardware and like sharing our designs with others.
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LitePCIe is mainly developed and maintained by EnjoyDigital.
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If you would like to know more about LitePCIe or if you are already a happy
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user and would like to extend it for your needs, EnjoyDigital can provide standard
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commercial support as well as consulting services.
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So feel free to contact us, we'd love to work with you! (and eventually shorten
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the list of the possible improvements :)
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[> Contact
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E-mail: florent [AT] enjoy-digital.fr
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