litex/examples/basic/fsm.py

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from migen.fhdl.std import *
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from migen.fhdl import verilog
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from migen.genlib.fsm import FSM, NextState
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class Example(Module):
def __init__(self):
self.s = Signal()
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myfsm = FSM()
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self.submodules += myfsm
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myfsm.act("FOO", self.s.eq(1), NextState("BAR"))
myfsm.act("BAR", self.s.eq(0), NextState("FOO"))
self.be = myfsm.before_entering("FOO")
self.ae = myfsm.after_entering("FOO")
self.bl = myfsm.before_leaving("FOO")
self.al = myfsm.after_leaving("FOO")
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example = Example()
print(verilog.convert(example, {example.s, example.be, example.ae, example.bl, example.al}))