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litex/misoclib/mxcrg/__init__.py

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Generate all clocks for the DDR PHY
2012-02-16 12:02:37 -05:00
from fractions import Fraction
Use migen.fhdl.std
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from migen.fhdl.std import *
Generate all clocks for the DDR PHY
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framebuffer: prepare for DVI out
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class MXCRG(Module):
Use new Mibuild generic_platform API
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def __init__(self, pads, outfreq1x):
Use new ClockDomain API
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self.clock_domains.cd_sys = ClockDomain()
use Migen s6ddrphy, generate sdram init_sequence in cif.py
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self.clock_domains.cd_sdram_half = ClockDomain()
self.clock_domains.cd_sdram_full_wr = ClockDomain()
self.clock_domains.cd_sdram_full_rd = ClockDomain()
Use new ClockDomain API
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self.clock_domains.cd_eth_rx = ClockDomain()
self.clock_domains.cd_eth_tx = ClockDomain()
framebuffer: prepare for DVI out
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self.clock_domains.cd_base50 = ClockDomain(reset_less=True)
Use new Mibuild generic_platform API
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self.clk4x_wr_strb = Signal()
self.clk4x_rd_strb = Signal()
###
Basic support for new clock domain and instance API
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Use new Mibuild generic_platform API
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infreq = 50*1000000
Basic support for new clock domain and instance API
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ratio = Fraction(outfreq1x)/Fraction(infreq)
in_period = float(Fraction(1000000000)/Fraction(infreq))
Mixxeo support
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self.specials += Instance("mxcrg",
Basic support for new clock domain and instance API
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Instance.Parameter("in_period", in_period),
Instance.Parameter("f_mult", ratio.numerator),
Instance.Parameter("f_div", ratio.denominator),
Use new Mibuild generic_platform API
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Instance.Input("clk50_pad", pads.clk50),
Instance.Input("trigger_reset", pads.trigger_reset),
Basic support for new clock domain and instance API
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Use new Mibuild generic_platform API
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Instance.Input("eth_rx_clk_pad", pads.eth_rx_clk),
Instance.Input("eth_tx_clk_pad", pads.eth_tx_clk),
Use Mibuild
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Basic support for new clock domain and instance API
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Instance.Output("sys_clk", self.cd_sys.clk),
Define clock domains instead of passing extra clocks as regular signals
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Instance.Output("sys_rst", self.cd_sys.rst),
use Migen s6ddrphy, generate sdram init_sequence in cif.py
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Instance.Output("clk2x_270", self.cd_sdram_half.clk),
Instance.Output("clk4x_wr", self.cd_sdram_full_wr.clk),
Instance.Output("clk4x_rd", self.cd_sdram_full_rd.clk),
Use Mibuild
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Instance.Output("eth_rx_clk", self.cd_eth_rx.clk),
Instance.Output("eth_tx_clk", self.cd_eth_tx.clk),
framebuffer: prepare for DVI out
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Instance.Output("base50_clk", self.cd_base50.clk),
Use new Mibuild generic_platform API
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Instance.Output("clk4x_wr_strb", self.clk4x_wr_strb),
Instance.Output("clk4x_rd_strb", self.clk4x_rd_strb),
Instance.Output("norflash_rst_n", pads.norflash_rst_n),
Instance.Output("ddr_clk_pad_p", pads.ddr_clk_p),
Instance.Output("ddr_clk_pad_n", pads.ddr_clk_n),
framebuffer: prepare for DVI out
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Instance.Output("eth_phy_clk_pad", pads.eth_phy_clk))