2013-05-22 11:11:09 -04:00
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from migen.fhdl.std import *
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2011-12-16 10:02:55 -05:00
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2015-04-13 14:45:35 -04:00
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2013-05-22 11:11:09 -04:00
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class Divider(Module):
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2015-04-13 14:07:07 -04:00
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def __init__(self, w):
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self.start_i = Signal()
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self.dividend_i = Signal(w)
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self.divisor_i = Signal(w)
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self.ready_o = Signal()
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self.quotient_o = Signal(w)
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self.remainder_o = Signal(w)
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2014-10-17 05:08:37 -04:00
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2015-04-13 14:07:07 -04:00
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###
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2014-10-17 05:08:37 -04:00
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2015-04-13 14:07:07 -04:00
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qr = Signal(2*w)
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counter = Signal(max=w+1)
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divisor_r = Signal(w)
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diff = Signal(w+1)
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2014-10-17 05:08:37 -04:00
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2015-04-13 14:07:07 -04:00
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self.comb += [
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self.quotient_o.eq(qr[:w]),
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self.remainder_o.eq(qr[w:]),
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self.ready_o.eq(counter == 0),
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diff.eq(qr[w-1:] - divisor_r)
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]
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self.sync += [
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If(self.start_i,
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counter.eq(w),
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qr.eq(self.dividend_i),
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divisor_r.eq(self.divisor_i)
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).Elif(~self.ready_o,
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If(diff[w],
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qr.eq(Cat(0, qr[:2*w-1]))
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).Else(
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qr.eq(Cat(1, qr[:w-1], diff[:w]))
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),
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counter.eq(counter - 1)
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)
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]
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