litex/miscope/miio.py

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from migen.fhdl.structure import *
from migen.bus import csr
from migen.bank import description, csrgen
from migen.bank.description import *
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class MiIo:
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#
# Definition
#
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def __init__(self, address, width, mode = "IO", interface=None):
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self.address = address
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self.width = width
self.mode = mode
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self.interface = interface
self.words = int(2**bits_for(width-1)/8)
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if "I" in self.mode:
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self.i = Signal(self.width)
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self.ireg = description.RegisterField("i", self.width, READ_ONLY, WRITE_ONLY)
self.ireg.field.w.name_override = "inputs"
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if "O" in self.mode:
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self.o = Signal(self.width)
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self.oreg = description.RegisterField("o", self.width)
self.oreg.field.r.name_override = "ouptuts"
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self.bank = csrgen.Bank([self.oreg, self.ireg], address=self.address)
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def get_fragment(self):
comb = []
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if "I" in self.mode:
comb += [self.ireg.field.w.eq(self.i)]
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if "O" in self.mode:
comb += [self.o.eq(self.oreg.field.r)]
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return Fragment(comb) + self.bank.get_fragment()
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#
#Driver
#
def write(self, data):
self.interface.write_n(self.address, data, self.width)
def read(self):
r = self.interface.read_n(self.address + self.words, self.width)
return r