litex/migen/test/support.py

14 lines
300 B
Python
Raw Normal View History

from migen import *
2013-11-29 03:47:32 -05:00
from migen.fhdl import verilog
2015-04-13 14:45:35 -04:00
class SimCase:
def setUp(self, *args, **kwargs):
self.tb = self.TestBench(*args, **kwargs)
2013-11-29 03:47:32 -05:00
def test_to_verilog(self):
verilog.convert(self.tb)
2013-11-29 03:47:32 -05:00
def run_with(self, generator):
2015-09-21 09:20:31 -04:00
run_simulation(self.tb, generator)