2015-01-16 14:25:11 -05:00
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__ _ __ _______ _________
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/ / (_) /____ / __/ _ /_ __/ _ |
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/ /__/ / __/ -_)\ \/ __ |/ / / __ |
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/____/_/\__/\__/___/_/ |_/_/ /_/ |_|
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Copyright 2014-2015 / Florent Kermarrec / florent@enjoy-digital.fr
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2015-01-16 17:52:41 -05:00
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A generic and configurable SATA1/2/3 core
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developed in partnership with M-Labs Ltd & HKU
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[> Features
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------------------
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PHY:
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- OOB, COMWAKE, COMINIT.
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- ALIGN inserter/remover and bytes alignment on K28.5.
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- 8B/10B encoding/decoding in transceiver.
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- Errors detection and reporting.
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- 1.5 / 3.0 / 6.0GBPs supported speeds.
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- 37.5 / 75 / 150MHz system clock.
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Core:
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Link:
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- CONT inserter/remover.
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- Scrambling/Descrambling of data.
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- CRC inserter/checker.
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- HOLD insertion/detection.
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- Errors detection and reporting.
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Transport/Command:
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- Easy to use user interface (Can be used with or without CPU).
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- 48 bits sector addressing.
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- 3 supported commands: READ_DMA(_EXT), WRITE_DMA(_EXT), IDENTIFY_DEVICE.
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- Errors detection and reporting.
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Frontend:
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- Configurable crossbar (simply use core.crossbar.get_port() to add a new port!)
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- Ports arbitration transparent to the user.
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- Synthetizable BIST.
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2014-09-22 06:33:23 -04:00
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[> Getting started
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------------------
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2015-01-16 14:25:11 -05:00
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1. Install Python3 and Xilinx's Vivado software.
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2. Obtain Migen and install it:
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git clone https://github.com/enjoy-digital/migen
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cd migen
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python3 setup.py install
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cd ..
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2014-09-22 06:33:23 -04:00
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2015-01-16 14:25:11 -05:00
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3. Obtain Miscope and install it:
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git clone https://github.com/enjoy-digital/miscope
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cd miscope
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python3 setup.py install
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cd ..
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4. Obtain MiSoC:
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git clone https://github.com/enjoy-digital/misoc --recursive
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5. Copy lite-sata in working directory and move to it.
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6. Build and load design:
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2014-09-22 06:33:23 -04:00
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make all
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2015-01-16 14:25:11 -05:00
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7. Test design:
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2015-01-16 17:52:41 -05:00
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go to test directory and run:
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2015-01-16 14:25:11 -05:00
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python3 bist.py
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[> Simulations :
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2015-01-16 17:52:41 -05:00
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Simulations are avalaible in ./lib/sata/test:
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2015-01-16 14:25:11 -05:00
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- crc_tb
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- scrambler_tb
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- phy_datapath_tb
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- link_tb
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- command_tb
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- bist_tb
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2015-01-16 16:49:34 -05:00
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hdd.py is a HDD model implementing all SATA layers.
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2015-01-16 17:52:41 -05:00
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To run a simulation, move to ./lib/sata/test and run:
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2015-01-16 14:25:11 -05:00
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make simulation_name
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2014-09-22 06:33:23 -04:00
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2015-01-16 14:25:11 -05:00
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[> Tests :
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2015-01-16 17:52:41 -05:00
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A synthetisable BIST is provided and can be controlled with ./test/bist.py
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By using Miscope and the provided ./test/test_link.py example you are able to
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visualize the internal logic of the design and even inject the captured data in
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the HDD model!
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2014-09-22 06:33:23 -04:00
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[> Contact
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E-mail: florent@enjoy-digital.fr
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