2012-02-16 12:02:37 -05:00
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from fractions import Fraction
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from migen.fhdl.structure import *
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2013-02-24 07:07:25 -05:00
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from migen.fhdl.specials import Instance
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2013-03-10 14:32:38 -04:00
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from migen.fhdl.module import Module
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2013-03-28 14:07:17 -04:00
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from migen.bank.description import *
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2012-02-16 12:02:37 -05:00
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2013-03-28 14:07:17 -04:00
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class M1CRG(Module, AutoReg):
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2013-03-26 12:57:17 -04:00
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def __init__(self, pads, outfreq1x):
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2013-03-15 14:17:05 -04:00
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self.clock_domains.cd_sys = ClockDomain()
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self.clock_domains.cd_sys2x_270 = ClockDomain()
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self.clock_domains.cd_sys4x_wr = ClockDomain()
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self.clock_domains.cd_sys4x_rd = ClockDomain()
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self.clock_domains.cd_eth_rx = ClockDomain()
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self.clock_domains.cd_eth_tx = ClockDomain()
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self.clock_domains.cd_vga = ClockDomain()
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2013-03-26 12:57:17 -04:00
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self.clk4x_wr_strb = Signal()
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self.clk4x_rd_strb = Signal()
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2013-03-28 14:07:17 -04:00
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self._r_cmd_data = RegisterField(10)
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self._r_send_cmd_data = RegisterRaw()
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self._r_send_go = RegisterRaw()
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self._r_status = RegisterField(3, READ_ONLY, WRITE_ONLY)
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2013-03-26 12:57:17 -04:00
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###
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2012-09-10 17:47:06 -04:00
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2013-03-26 12:57:17 -04:00
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infreq = 50*1000000
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2012-09-10 17:47:06 -04:00
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ratio = Fraction(outfreq1x)/Fraction(infreq)
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in_period = float(Fraction(1000000000)/Fraction(infreq))
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2013-03-28 14:07:17 -04:00
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vga_progdata = Signal()
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vga_progen = Signal()
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vga_progdone = Signal()
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vga_locked = Signal()
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2013-03-26 12:57:17 -04:00
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self.specials += Instance("m1crg",
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2012-09-10 17:47:06 -04:00
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Instance.Parameter("in_period", in_period),
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Instance.Parameter("f_mult", ratio.numerator),
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Instance.Parameter("f_div", ratio.denominator),
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2013-03-26 12:57:17 -04:00
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Instance.Input("clk50_pad", pads.clk50),
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Instance.Input("trigger_reset", pads.trigger_reset),
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2012-09-10 17:47:06 -04:00
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2013-03-26 12:57:17 -04:00
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Instance.Input("eth_rx_clk_pad", pads.eth_rx_clk),
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Instance.Input("eth_tx_clk_pad", pads.eth_tx_clk),
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2013-02-11 12:23:06 -05:00
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2012-09-10 17:47:06 -04:00
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Instance.Output("sys_clk", self.cd_sys.clk),
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2012-09-10 18:21:07 -04:00
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Instance.Output("sys_rst", self.cd_sys.rst),
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Instance.Output("clk2x_270", self.cd_sys2x_270.clk),
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Instance.Output("clk4x_wr", self.cd_sys4x_wr.clk),
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Instance.Output("clk4x_rd", self.cd_sys4x_rd.clk),
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2013-02-11 12:23:06 -05:00
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Instance.Output("eth_rx_clk", self.cd_eth_rx.clk),
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Instance.Output("eth_tx_clk", self.cd_eth_tx.clk),
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2013-03-26 12:57:17 -04:00
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Instance.Output("vga_clk", self.cd_vga.clk),
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Instance.Output("clk4x_wr_strb", self.clk4x_wr_strb),
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Instance.Output("clk4x_rd_strb", self.clk4x_rd_strb),
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Instance.Output("norflash_rst_n", pads.norflash_rst_n),
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Instance.Output("ddr_clk_pad_p", pads.ddr_clk_p),
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Instance.Output("ddr_clk_pad_n", pads.ddr_clk_n),
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Instance.Output("eth_phy_clk_pad", pads.eth_phy_clk),
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2013-03-28 14:07:17 -04:00
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Instance.Output("vga_clk_pad", pads.vga_clk),
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Instance.Input("vga_progclk", ClockSignal()),
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Instance.Input("vga_progdata", vga_progdata),
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Instance.Input("vga_progen", vga_progen),
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Instance.Output("vga_progdone", vga_progdone),
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Instance.Output("vga_locked", vga_locked))
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remaining_bits = Signal(max=11)
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transmitting = Signal()
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self.comb += transmitting.eq(remaining_bits != 0)
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sr = Signal(10)
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self.sync += [
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If(self._r_send_cmd_data.re,
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remaining_bits.eq(10),
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sr.eq(self._r_cmd_data.field.r)
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).Elif(transmitting,
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remaining_bits.eq(remaining_bits - 1),
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sr.eq(sr[1:])
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)
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]
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self.comb += [
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vga_progdata.eq(transmitting & sr[0]),
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vga_progen.eq(transmitting | self._r_send_go.re)
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]
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# enforce gap between commands
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busy_counter = Signal(max=14)
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busy = Signal()
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self.comb += busy.eq(busy_counter != 0)
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self.sync += If(self._r_send_cmd_data.re,
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busy_counter.eq(13)
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).Elif(busy,
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busy_counter.eq(busy_counter - 1)
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)
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self.comb += self._r_status.field.w.eq(Cat(busy, vga_progdone, vga_locked))
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