2015-02-28 04:53:51 -05:00
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from misoclib.mem.litesata.common import *
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from misoclib.mem.litesata.phy import *
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from misoclib.mem.litesata.core import *
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from misoclib.mem.litesata.frontend import *
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2015-01-16 17:52:41 -05:00
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from migen.bank.description import *
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class LiteSATA(Module, AutoCSR):
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2015-01-21 17:11:38 -05:00
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def __init__(self, phy, buffer_depth=2*fis_max_dwords,
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2015-01-16 17:52:41 -05:00
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with_bist=False, with_bist_csr=False):
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# phy
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self.phy = phy
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# core
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2015-01-22 10:02:41 -05:00
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self.submodules.core = LiteSATACore(self.phy, buffer_depth)
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2015-01-16 17:52:41 -05:00
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# frontend
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2015-01-22 10:02:41 -05:00
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self.submodules.crossbar = LiteSATACrossbar(self.core)
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if with_bist:
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self.submodules.bist = LiteSATABIST(self.crossbar, with_bist_csr)
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2015-01-16 17:52:41 -05:00
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