litex/migen/actorlib/spi.py

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# Simple Processor Interface
from migen.fhdl.structure import *
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from migen.fhdl.specials import Memory
from migen.bank.description import *
from migen.flow.actor import *
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# layout is a list of tuples, either:
# - (name, nbits, [reset value], [alignment bits])
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# - (name, sublayout)
def _convert_layout(layout):
r = []
for element in layout:
if isinstance(element[1], list):
r.append((element[0], _convert_layout(element[1])))
else:
r.append((element[0], element[1]))
return r
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def _create_csrs_assign(layout, target, atomic, prefix=""):
csrs = []
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assigns = []
for element in layout:
if isinstance(element[1], list):
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r_csrs, r_assigns = _create_csrs_assign(element[1],
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atomic,
getattr(target, element[0]),
element[0] + "_")
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csrs += r_csrs
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assigns += r_assigns
else:
name = element[0]
nbits = element[1]
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if len(element) > 2:
reset = element[2]
else:
reset = 0
if len(element) > 3:
alignment = element[3]
else:
alignment = 0
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reg = CSRStorage(nbits + alignment, reset=reset, atomic_write=atomic, name=prefix + name)
csrs.append(reg)
assigns.append(getattr(target, name).eq(reg.storage[alignment:]))
return csrs, assigns
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(MODE_EXTERNAL, MODE_SINGLE_SHOT, MODE_CONTINUOUS) = range(3)
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class SingleGenerator(Module):
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def __init__(self, layout, mode):
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self.source = Source(_convert_layout(layout))
self.busy = Signal()
self._csrs, assigns = _create_csrs_assign(layout, self.source.payload,
mode != MODE_SINGLE_SHOT)
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if mode == MODE_EXTERNAL:
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trigger = self.trigger = Signal()
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elif mode == MODE_SINGLE_SHOT:
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shoot = CSR()
self._csrs.insert(0, shoot)
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trigger = shoot.re
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elif mode == MODE_CONTINUOUS:
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enable = CSRStorage()
self._csrs.insert(0, enable)
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trigger = enable.storage
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else:
raise ValueError
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self.comb += self.busy.eq(self.source.stb)
stmts = [self.source.stb.eq(trigger)] + assigns
self.sync += [If(self.source.ack | ~self.source.stb, *stmts)]
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def get_csrs(self):
return self._csrs
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class Collector(Module, AutoCSR):
def __init__(self, layout, depth=1024):
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self.sink = Sink(layout)
self.busy = Signal()
self._depth = depth
self._dw = sum(len(s) for s in self.token("sink").flatten())
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self._r_wa = CSRStorage(bits_for(self._depth-1), write_from_dev=True)
self._r_wc = CSRStorage(bits_for(self._depth), write_from_dev=True, atomic_write=True)
self._r_ra = CSRStorage(bits_for(self._depth-1))
self._r_rd = CSRStatus(self._dw)
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###
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mem = Memory(self._dw, self._depth)
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self.specials += mem
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wp = mem.get_port(write_capable=True)
rp = mem.get_port()
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self.comb += [
self.busy.eq(0),
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If(self._r_wc.r != 0,
self.endpoints["sink"].ack.eq(1),
If(self.endpoints["sink"].stb,
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self._r_wa.we.eq(1),
self._r_wc.we.eq(1),
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wp.we.eq(1)
)
),
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self._r_wa.dat_w.eq(self._r_wa.storage + 1),
self._r_wc.dat_w.eq(self._r_wc.storage - 1),
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wp.adr.eq(self._r_wa.storage),
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wp.dat_w.eq(self.token("sink").raw_bits()),
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rp.adr.eq(self._r_ra.storage),
self._r_rd.status.eq(rp.dat_r)
]