Fix various errors from new bitwidth/signedness system conversion

This commit is contained in:
Sebastien Bourdeauducq 2012-11-29 23:36:55 +01:00
parent 261166d92b
commit 70e97e0456
3 changed files with 6 additions and 6 deletions

View File

@ -5,7 +5,7 @@ from migen.bank.description import *
from migen.flow.actor import *
# layout is a list of tuples, either:
# - (name, bv, [reset value], [alignment bits])
# - (name, nbits, [reset value], [alignment bits])
# - (name, sublayout)
def _convert_layout(layout):
@ -30,7 +30,7 @@ def _create_registers_assign(layout, target, atomic, prefix=""):
assigns += r_assigns
else:
name = element[0]
bv = element[1]
nbits = element[1]
if len(element) > 2:
reset = element[2]
else:
@ -39,7 +39,7 @@ def _create_registers_assign(layout, target, atomic, prefix=""):
alignment = element[3]
else:
alignment = 0
reg = RegisterField(prefix + name, bv.width + alignment,
reg = RegisterField(prefix + name, nbits + alignment,
reset=reset, atomic_write=atomic)
registers.append(reg)
assigns.append(getattr(target, name).eq(reg.field.r[alignment:]))

View File

@ -6,7 +6,7 @@ class RoundRobin:
def __init__(self, n, switch_policy=SP_WITHDRAW):
self.n = n
self.request = Signal(max=self.n)
self.grant = Signal(self.bn)
self.grant = Signal(max=self.n)
self.switch_policy = switch_policy
if self.switch_policy == SP_CE:
self.ce = Signal()

View File

@ -78,7 +78,7 @@ def _printexpr(ns, node):
l = [_printexpr(ns, v)[0] for v in reversed(node.l)]
return "{" + ", ".join(l) + "}", False
elif isinstance(node, Replicate):
return "{" + str(node.n) + "{" + _printexpr(ns, node.v) + "}}", False
return "{" + str(node.n) + "{" + _printexpr(ns, node.v)[0] + "}}", False
else:
raise TypeError
@ -223,7 +223,7 @@ def _printinstances(f, ns, clock_domains):
firstp = False
r += "\t." + p.name + "("
if isinstance(p.value, (int, bool)):
r += _printintbool(p.value)
r += _printintbool(p.value)[0]
elif isinstance(p.value, float):
r += str(p.value)
elif isinstance(p.value, str):