2011-12-16 15:30:22 -05:00
|
|
|
from migen.fhdl.structure import *
|
2011-12-13 11:33:12 -05:00
|
|
|
from migen.bus import wishbone
|
|
|
|
|
2012-01-21 06:25:22 -05:00
|
|
|
class LM32:
|
2011-12-13 11:33:12 -05:00
|
|
|
def __init__(self):
|
2012-01-27 16:21:08 -05:00
|
|
|
self.ibus = i = wishbone.Master()
|
|
|
|
self.dbus = d = wishbone.Master()
|
2011-12-18 16:02:05 -05:00
|
|
|
self.interrupt = Signal(BV(32))
|
|
|
|
self.ext_break = Signal()
|
2011-12-16 15:30:22 -05:00
|
|
|
self._inst = Instance("lm32_top",
|
2012-01-13 11:28:58 -05:00
|
|
|
[("I_ADR_O", BV(32)),
|
2011-12-13 11:33:12 -05:00
|
|
|
("I_DAT_O", i.dat_o),
|
|
|
|
("I_SEL_O", i.sel_o),
|
|
|
|
("I_CYC_O", i.cyc_o),
|
|
|
|
("I_STB_O", i.stb_o),
|
|
|
|
("I_WE_O", i.we_o),
|
|
|
|
("I_CTI_O", i.cti_o),
|
2011-12-16 15:30:22 -05:00
|
|
|
("I_LOCK_O", BV(1)),
|
2011-12-13 11:33:12 -05:00
|
|
|
("I_BTE_O", i.bte_o),
|
2012-01-13 11:28:58 -05:00
|
|
|
("D_ADR_O", BV(32)),
|
2011-12-13 11:33:12 -05:00
|
|
|
("D_DAT_O", d.dat_o),
|
|
|
|
("D_SEL_O", d.sel_o),
|
|
|
|
("D_CYC_O", d.cyc_o),
|
|
|
|
("D_STB_O", d.stb_o),
|
|
|
|
("D_WE_O", d.we_o),
|
|
|
|
("D_CTI_O", d.cti_o),
|
2011-12-16 15:30:22 -05:00
|
|
|
("D_LOCK_O", BV(1)),
|
2011-12-13 11:33:12 -05:00
|
|
|
("D_BTE_O", d.bte_o)],
|
|
|
|
[("interrupt", self.interrupt),
|
|
|
|
#("ext_break", self.ext_break),
|
|
|
|
("I_DAT_I", i.dat_i),
|
|
|
|
("I_ACK_I", i.ack_i),
|
|
|
|
("I_ERR_I", i.err_i),
|
2011-12-16 15:30:22 -05:00
|
|
|
("I_RTY_I", BV(1)),
|
2011-12-13 11:33:12 -05:00
|
|
|
("D_DAT_I", d.dat_i),
|
|
|
|
("D_ACK_I", d.ack_i),
|
|
|
|
("D_ERR_I", d.err_i),
|
2011-12-16 15:30:22 -05:00
|
|
|
("D_RTY_I", BV(1))],
|
2011-12-13 11:33:12 -05:00
|
|
|
[],
|
|
|
|
"clk_i",
|
|
|
|
"rst_i",
|
|
|
|
"lm32")
|
|
|
|
|
2011-12-16 10:02:49 -05:00
|
|
|
def get_fragment(self):
|
2011-12-13 11:33:12 -05:00
|
|
|
comb = [
|
2011-12-16 15:30:22 -05:00
|
|
|
self._inst.ins["I_RTY_I"].eq(0),
|
2012-01-13 11:28:58 -05:00
|
|
|
self._inst.ins["D_RTY_I"].eq(0),
|
|
|
|
self.ibus.adr_o.eq(self._inst.outs["I_ADR_O"][2:]),
|
|
|
|
self.dbus.adr_o.eq(self._inst.outs["D_ADR_O"][2:])
|
2011-12-13 11:33:12 -05:00
|
|
|
]
|
2011-12-16 15:30:22 -05:00
|
|
|
return Fragment(comb=comb, instances=[self._inst])
|