Support the new FHDL syntax
This commit is contained in:
Sebastien Bourdeauducq
parent
ca68097ef6
commit
738b45dcbd
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@ -1,13 +1,13 @@
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from migen.fhdl import structure as f
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from migen.fhdl.structure import *
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from migen.bus import wishbone
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class Inst:
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def __init__(self):
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self.ibus = i = wishbone.Master("lm32i")
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self.dbus = d = wishbone.Master("lm32d")
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f.declare_signal(self, "interrupt", f.BV(32))
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f.declare_signal(self, "ext_break")
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self._inst = f.Instance("lm32_top",
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declare_signal(self, "interrupt", BV(32))
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declare_signal(self, "ext_break")
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self._inst = Instance("lm32_top",
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[("I_ADR_O", i.adr_o),
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("I_DAT_O", i.dat_o),
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("I_SEL_O", i.sel_o),
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@ -15,7 +15,7 @@ class Inst:
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("I_STB_O", i.stb_o),
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("I_WE_O", i.we_o),
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("I_CTI_O", i.cti_o),
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("I_LOCK_O", f.BV(1)),
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("I_LOCK_O", BV(1)),
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("I_BTE_O", i.bte_o),
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("D_ADR_O", d.adr_o),
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("D_DAT_O", d.dat_o),
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@ -24,18 +24,18 @@ class Inst:
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("D_STB_O", d.stb_o),
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("D_WE_O", d.we_o),
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("D_CTI_O", d.cti_o),
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("D_LOCK_O", f.BV(1)),
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("D_LOCK_O", BV(1)),
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("D_BTE_O", d.bte_o)],
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[("interrupt", self.interrupt),
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#("ext_break", self.ext_break),
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("I_DAT_I", i.dat_i),
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("I_ACK_I", i.ack_i),
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("I_ERR_I", i.err_i),
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("I_RTY_I", f.BV(1)),
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("I_RTY_I", BV(1)),
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("D_DAT_I", d.dat_i),
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("D_ACK_I", d.ack_i),
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("D_ERR_I", d.err_i),
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("D_RTY_I", f.BV(1))],
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("D_RTY_I", BV(1))],
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[],
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"clk_i",
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"rst_i",
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@ -43,7 +43,7 @@ class Inst:
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def get_fragment(self):
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comb = [
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f.Assign(self._inst.ins["I_RTY_I"], 0),
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f.Assign(self._inst.ins["D_RTY_I"], 0)
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self._inst.ins["I_RTY_I"].eq(0),
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self._inst.ins["D_RTY_I"].eq(0)
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]
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return f.Fragment(comb=comb, instances=[self._inst])
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return Fragment(comb=comb, instances=[self._inst])
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@ -1,32 +1,32 @@
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from functools import partial
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from migen.fhdl import structure as f
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from migen.fhdl.structure import *
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from migen.bus import wishbone
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from migen.corelogic import timeline
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class Inst:
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def __init__(self, adr_width, rd_timing):
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self.bus = wishbone.Slave("norflash")
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d = partial(f.declare_signal, self)
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d("adr", f.BV(adr_width-1))
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d("d", f.BV(16))
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d = partial(declare_signal, self)
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d("adr", BV(adr_width-1))
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d("d", BV(16))
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d("oe_n")
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d("we_n")
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d("ce_n")
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d("rst_n")
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self.timeline = timeline.Inst(self.bus.cyc_i & self.bus.stb_i,
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[(0, [f.Assign(self.adr, f.Cat(0, self.bus.adr_i[2:adr_width]))]),
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[(0, [self.adr.eq(Cat(0, self.bus.adr_i[2:adr_width]))]),
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(rd_timing, [
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f.Assign(self.bus.dat_o[16:], self.d),
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f.Assign(self.adr, f.Cat(1, self.bus.adr_i[2:adr_width]))]),
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self.bus.dat_o[16:].eq(self.d),
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self.adr.eq(Cat(1, self.bus.adr_i[2:adr_width]))]),
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(2*rd_timing, [
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f.Assign(self.bus.dat_o[:16], self.d),
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f.Assign(self.bus.ack_o, 1)]),
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self.bus.dat_o[:16].eq(self.d),
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self.bus.ack_o.eq(1)]),
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(2*rd_timing+1, [
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f.Assign(self.bus.ack_o, 0)])])
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self.bus.ack_o.eq(0)])])
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def get_fragment(self):
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comb = [f.Assign(self.oe_n, 0), f.Assign(self.we_n, 1),
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f.Assign(self.ce_n, 0), f.Assign(self.rst_n, 1)]
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return f.Fragment(comb, pads={self.adr, self.d, self.oe_n, self.we_n, self.ce_n, self.rst_n}) \
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comb = [self.oe_n.eq(0), self.we_n.eq(1),
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self.ce_n.eq(0), self.rst_n.eq(1)]
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return Fragment(comb, pads={self.adr, self.d, self.oe_n, self.we_n, self.ce_n, self.rst_n}) \
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+ self.timeline.get_fragment()
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@ -1,14 +1,14 @@
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from migen.fhdl import structure as f
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from migen.fhdl.structure import *
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from migen.bus import csr
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class Inst:
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def __init__(self, csr_addr, clk_freq, baud=115200, break_en_default=f.Constant(0)):
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def __init__(self, csr_addr, clk_freq, baud=115200, break_en_default=Constant(0)):
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self.bus = csr.Slave("uart")
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f.declare_signal(self, "tx")
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f.declare_signal(self, "rx")
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f.declare_signal(self, "irq")
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f.declare_signal(self, "brk")
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self._inst = f.Instance("uart",
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declare_signal(self, "tx")
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declare_signal(self, "rx")
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declare_signal(self, "irq")
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declare_signal(self, "brk")
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self._inst = Instance("uart",
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[("csr_do", self.bus.d_o),
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("uart_tx", self.tx),
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("irq", self.irq),
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@ -17,7 +17,7 @@ class Inst:
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("csr_we", self.bus.we_i),
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("csr_di", self.bus.d_i),
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("uart_rx", self.rx)],
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[("csr_addr", f.Constant(csr_addr, f.BV(4))),
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[("csr_addr", Constant(csr_addr, BV(4))),
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("clk_freq", clk_freq),
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("baud", baud),
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("break_en_default", break_en_default)],
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@ -25,4 +25,4 @@ class Inst:
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"sys_rst")
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def get_fragment(self):
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return f.Fragment(instances=[self._inst], pads={self.tx, self.rx})
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return Fragment(instances=[self._inst], pads={self.tx, self.rx})
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@ -1,5 +1,4 @@
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from migen.fhdl import verilog
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from migen.fhdl import structure as f
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from migen.bus import wishbone
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from milkymist import norflash
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