57 lines
2.0 KiB
Python
57 lines
2.0 KiB
Python
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from mibuild.generic_platform import *
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from mibuild.xilinx_ise import XilinxISEPlatform, CRG_DS
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_io = [
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# System clock (Differential 200MHz)
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("clk200", 0,
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Subsignal("p", Pins("J9"), IOStandard("LVDS_25"), Misc("DIFF_TERM=TRUE")),
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Subsignal("n", Pins("H9"), IOStandard("LVDS_25"), Misc("DIFF_TERM=TRUE"))
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),
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# User clock (66MHz)
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("clk66", 0, Pins("U23"), IOStandard("LVCMOS25")),
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# CPU reset switch
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("cpu_reset", 0, Pins("H10"), IOStandard("SSTL15")),
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# LEDs
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("user_led", 0, Pins("AC22"), IOStandard("LVCMOS25"), Misc("SLEW=SLOW")),
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("user_led", 1, Pins("AC24"), IOStandard("LVCMOS25"), Misc("SLEW=SLOW")),
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("user_led", 2, Pins("AE22"), IOStandard("LVCMOS25"), Misc("SLEW=SLOW")),
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("user_led", 3, Pins("AE23"), IOStandard("LVCMOS25"), Misc("SLEW=SLOW")),
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("user_led", 4, Pins("AB23"), IOStandard("LVCMOS25"), Misc("SLEW=SLOW")),
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("user_led", 5, Pins("AG23"), IOStandard("LVCMOS25"), Misc("SLEW=SLOW")),
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("user_led", 6, Pins("AE24"), IOStandard("LVCMOS25"), Misc("SLEW=SLOW")),
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("user_led", 7, Pins("AD24"), IOStandard("LVCMOS25"), Misc("SLEW=SLOW")),
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# USB-to-UART
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("serial", 0,
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Subsignal("tx", Pins("J25"), IOStandard("LVCMOS25")),
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Subsignal("rx", Pins("J24"), IOStandard("LVCMOS25"))
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),
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# 10/100/1000 Tri-Speed Ethernet PHY
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("eth_clocks", 0,
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Subsignal("rx", Pins("AP11")),
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Subsignal("tx", Pins("AD12")),
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IOStandard("LVCMOS25")
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),
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("eth", 0,
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Subsignal("rst_n", Pins("AH13")),
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Subsignal("dv", Pins("AM13")),
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Subsignal("rx_er", Pins("AG12")),
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Subsignal("rx_data", Pins("AN13", "AF14", "AE14", "AN12", "AM12", "AD11", "AC12", "AC13")),
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Subsignal("tx_en", Pins("AJ10")),
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Subsignal("tx_er", Pins("AH10")),
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Subsignal("tx_data", Pins("AM11", "AL11", "AG10", "AG11", "AL10", "AM10", "AE11", "AF11")),
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Subsignal("col", Pins("AK13")),
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Subsignal("crs", Pins("AL13")),
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IOStandard("LVCMOS25")
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)
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]
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class Platform(XilinxISEPlatform):
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def __init__(self):
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XilinxISEPlatform.__init__(self, "xc6vlx240t-ff1156-1", _io,
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lambda p: CRG_DS(p, "clk200", "user_btn", 5.0))
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