Sebastien Bourdeauducq 7a2f31b2e8 platforms/papilio_pro: no reset signal by default		2013-05-07 19:10:18 +02:00
..
platforms	platforms/papilio_pro: no reset signal by default	2013-05-07 19:10:18 +02:00
__init__.py	Initial version	2013-02-07 22:07:30 +01:00
altera_quartus.py	altera_quartus: fix clock domain name	2013-03-26 23:05:46 +01:00
crg.py	crg: support for resetless system clock domain	2013-05-07 19:09:56 +02:00
generic_platform.py	Support for platform info	2013-03-26 19:17:35 +01:00
tools.py	Support adding Verilog/VHDL files	2013-02-08 20:25:20 +01:00
xilinx_ise.py	crg: support for resetless system clock domain	2013-05-07 19:09:56 +02:00