litex/examples/basic/memory.py

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from migen.fhdl.structure import *
from migen.fhdl import verilog
d = 100
d_b = bits_for(d-1)
w = 32
a1 = Signal(BV(d_b))
d1 = Signal(BV(w))
we1 = Signal(BV(4))
dw1 = Signal(BV(w))
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re = Signal()
p1 = MemoryPort(a1, d1, we1, dw1, we_granularity=8)
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a2 = Signal(BV(d_b))
d2 = Signal(BV(w))
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re2 = Signal()
p2 = MemoryPort(a2, d2, re=re2, clock_domain="rd")
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mem = Memory(w, d, p1, p2, init=[5, 18, 32])
f = Fragment(memories=[mem])
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v = verilog.convert(f, ios={a1, d1, we1, dw1, a2, d2, re2})
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print(v)