litex/misoclib/mem/litesata/frontend/arbiter.py

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from misoclib.mem.litesata.common import *
from misoclib.mem.litesata.frontend.common import *
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from migen.genlib.roundrobin import *
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class LiteSATAArbiter(Module):
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def __init__(self, users, master):
self.rr = RoundRobin(len(users))
self.submodules += self.rr
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self.grant = self.rr.grant
cases = {}
for i, slave in enumerate(users):
sink, source = slave.sink, slave.source
start = Signal()
done = Signal()
ongoing = Signal()
self.comb += [
start.eq(sink.stb & sink.sop),
done.eq(source.stb & source.last & source.eop & source.ack)
]
self.sync += \
If(start,
ongoing.eq(1)
).Elif(done,
ongoing.eq(0)
)
self.comb += self.rr.request[i].eq((start | ongoing) & ~done)
cases[i] = [users[i].connect(master)]
self.comb += Case(self.grant, cases)