2015-01-27 18:33:26 -05:00
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from liteethernet.common import *
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from liteethernet.mac.common import *
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from liteethernet.mac.preamble import PreambleInserter, PreambleChecker
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from liteethernet.mac.crc import CRC32Inserter, CRC32Checker
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from liteethernet.mac.last_be import TXLastBE, RXLastBE
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class LiteEthernetMACCore(Module, AutoCSR):
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def __init__(self, phy, with_hw_preamble_crc=True, endianness="be"):
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# Preamble / CRC (optional)
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if with_hw_preamble_crc:
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self._hw_preamble_crc = CSRStatus(reset=1)
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# Preamble insert/check
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preamble_inserter = PreambleInserter(phy.dw)
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preamble_checker = PreambleChecker(phy.dw)
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self.submodules += RenameClockDomains(preamble_inserter, "eth_tx")
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self.submodules += RenameClockDomains(preamble_checker, "eth_rx")
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# CRC insert/check
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crc32_inserter = CRC32Inserter(eth_description(phy.dw))
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crc32_checker = CRC32Checker(eth_description(phy.dw))
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self.submodules += RenameClockDomains(crc32_inserter, "eth_tx")
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self.submodules += RenameClockDomains(crc32_checker, "eth_rx")
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# Delimiters
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tx_last_be = TXLastBE(phy.dw)
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rx_last_be = RXLastBE(phy.dw)
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self.submodules += RenameClockDomains(tx_last_be, "eth_tx")
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self.submodules += RenameClockDomains(rx_last_be, "eth_rx")
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# Converters
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reverse = endianness == "be"
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tx_converter = Converter(eth_description(32), eth_description(phy.dw), reverse=reverse)
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rx_converter = Converter(eth_description(phy.dw), eth_description(32), reverse=reverse)
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self.submodules += RenameClockDomains(tx_converter, "eth_tx")
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self.submodules += RenameClockDomains(rx_converter, "eth_rx")
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# Cross Domain Crossing
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tx_cdc = AsyncFIFO(eth_description(32), 4)
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rx_cdc = AsyncFIFO(eth_description(32), 4)
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self.submodules += RenameClockDomains(tx_cdc, {"write": "sys", "read": "eth_tx"})
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self.submodules += RenameClockDomains(rx_cdc, {"write": "eth_rx", "read": "sys"})
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# Graph
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if with_hw_preamble_crc:
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rx_pipeline = [phy, preamble_checker, crc32_checker, rx_last_be, rx_converter, rx_cdc]
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tx_pipeline = [tx_cdc, tx_converter, tx_last_be, crc32_inserter, preamble_inserter, phy]
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else:
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rx_pipeline = [phy, rx_last_be, rx_converter, rx_cdc]
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tx_pipeline = [tx_cdc, tx_converter, tx_last_be, phy]
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self.submodules.rx_pipeline = Pipeline(*rx_pipeline)
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self.submodules.tx_pipeline = Pipeline(*tx_pipeline)
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self.sink, self.source = self.tx_pipeline.sink, self.rx_pipeline.source
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