40 lines
1.4 KiB
Python
40 lines
1.4 KiB
Python
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from liteethernet.common import *
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from liteethernet.mac import LiteEthernetMAC
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class LiteEthernetMACWishboneInterface(Module, AutoCSR):
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def __init__(self, nrxslots=2, ntxslots=2):
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self.sink = Sink(mac_description(dw))
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self.source = Source(max_description(dw))
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self.bus = wishbone.Interface()
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###
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# SRAM Storage
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sram_depth = buffer_depth//(32//8)
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self.submodules.sram_writer = SRAMWriter(sram_depth, nrxslots)
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self.submodules.sram_reader = SRAMReader(sram_depth, ntxslots)
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self.submodules.ev = SharedIRQ(self.sram_writer.ev, self.sram_reader.ev)
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self.comb += [
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Record.connect(self.sink, self.sram_writer.sink),
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Record.connect(self.sram_reader.source, self.source)
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]
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# Interface
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wb_rx_sram_ifs = [wishbone.SRAM(self.sram_writer.mems[n], read_only=True)
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for n in range(nrxslots)]
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# TODO: FullMemoryWE should move to Mibuild
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wb_tx_sram_ifs = [FullMemoryWE(wishbone.SRAM(self.sram_reader.mems[n], read_only=False))
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for n in range(ntxslots)]
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wb_sram_ifs = wb_rx_sram_ifs + wb_tx_sram_ifs
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wb_slaves = []
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decoderoffset = log2_int(sram_depth)
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decoderbits = log2_int(len(wb_sram_ifs))
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for n, wb_sram_if in enumerate(wb_sram_ifs):
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def slave_filter(a, v=n):
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return a[decoderoffset:decoderoffset+decoderbits] == v
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wb_slaves.append((slave_filter, wb_sram_if.bus))
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self.submodules += wb_sram_if
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wb_con = wishbone.Decoder(self.bus, wb_slaves, register=True)
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self.submodules += wb_con
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