litex/migen/bus/csr.py

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from migen.fhdl.structure import *
from migen.bus.simple import *
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from migen.bus.transactions import *
from migen.sim.generic import PureSimulable
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data_width = 8
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class Interface(SimpleInterface):
def __init__(self):
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super().__init__(Description(
(M_TO_S, "adr", 14),
(M_TO_S, "we", 1),
(M_TO_S, "dat_w", data_width),
(S_TO_M, "dat_r", data_width)))
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class Interconnect(SimpleInterconnect):
pass
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class Initiator(PureSimulable):
def __init__(self, generator):
self.generator = generator
self.bus = Interface()
self.transaction = None
self.done = False
def do_simulation(self, s):
if not self.done:
if self.transaction is not None:
if isinstance(self.transaction, TRead):
self.transaction.data = s.rd(self.bus.dat_r)
else:
s.wr(self.bus.we, 0)
try:
self.transaction = next(self.generator)
except StopIteration:
self.transaction = None
self.done = True
if self.transaction is not None:
s.wr(self.bus.adr, self.transaction.address)
if isinstance(self.transaction, TWrite):
s.wr(self.bus.we, 1)
s.wr(self.bus.dat_w, self.transaction.data)